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PRODUCTS
Low Power, High Performance, High Reliability
LittleBee Flash Based FPGAs

GOWIN’s LittleBee® product family offers flash based, non-volatile FPGAs with an abundance of logic resources, multiple IO standards, embedded RAM, DSPs, PLLs, embedded security and additional user flash while being optimized for low power, low cost and small footprint applications requiring instant-on, high IO count, high throughput and low latency programmable computing. 

As a result, LittleBee® FPGAs are leading the industry in I/O intensive source synchronous interfacing and bridging applications such as MIPI CSI-2, MIPI DSI, USB 2.0, Ethernet, HDMI, MIPI I3C and more. They are also an ideal candidate for hardware management applications offering instant-on booting and built-in security functions.

The LittleBee® FPGA family is complimented by multiple innovative product line sub-features such as extended memory, hardened ARM Cortex-M processor cores, security and Bluetooth LE expanding its capabilities and usage compared to traditional FPGA products.

 

GOWIN Semiconductor also provides highly optimized and easy to use FPGA development software supporting the LittleBee® product family including synthesis, mapping, placement, routing and bitstream generation along with programming tools, embedded logic analyzer, and power calculator. 


 

LittleBee FPGA Product Features:

    • Small Form Factor

-As small as 2.3x2.4mm2

    • Embedded Flash

-Bitstream

-User

    • Extensive Pipeline Computing Resources

-Higher DSP Ratio

-Higher RAM Ratio

    • Flexible Programming Interface

-JTAG, MSPI, SSPI, I2C, CPU

-Multi-Boot

    • Serialized Interface Support

-MIPI CSI-2, MIPI DSI, LVDS, HDMI

-USB 2.0, PCI, Ethernet

-DDR3, HyperRAM, PSRAM

    • Embedded Security

- Bitstream Encryption

- Device Locking

    • Extension Features

- Integrated PSRAM

-Hardened ARM Cortex-M3 and Synopsys ARC MCU Cores

-Bluetooth Low Energy Transceiver

-PUF Based Asynchronous Application Security

-AEC-100Q Automotive Qualified

GW1N Series Table

 

Device GW1N-1 GW1N-1P5 GW1N-2 GW1N-4 GW1N-9
LUT4 1,152 1,584 2,304 4,608 8,640
Flip-Flop (FF) 864 1,584 2016 3,456 6,480
Shadow SRAM Capacity(bits) 0 12,672 18,432 0 17,280
Block SRAM Capacity(bits) 72K 72K 72K 180K 468K
Number of BSRAM 4 4 4 10 26
User Flash (bits) 96K 96K 96K 256K 608K
18 x18 multiplier 0 0 0 16 20
PLLs 1 1 1 2 2
Total Number of I/O Banks 4 6 6 4 4
Max. I/O 120 125 125 218 276
Core Voltage (LV) 1.2V 1.2V 1.2V 1.2V 1.2V
Core Voltage(UV)

1.8V-3.3V

1.8V-3.3V

1.8V-3.3V

2.5V-3.3V 2.5V-3.3V

 


 

Package Options, Availible User I/O, (and LVDS Pairs):

GW1N-1GW1N-1S

Package Pitch (mm) Size (mm) GW1N-1 GW1N-1P5 GW1N-2 GW1N-4 GW1N-9 Identifier

CS30

0.4

2.3 x 2.4

24

-

-

-

-

 

QN32

0.5

5 x 5

-

-

21 (1)

24(3)

-

 

QN32X

0.5

5 x 5

-

-

21 (1)

-

-

 X

FN32

0.4

4 x 4

-

-

-

-

-

 

CS42

0.4

2.4 x 2.9

-

 

24  (7)

-

-

 

CS42H

0.4

2.4 x 2.9

-

-

36(3)

-

-

 H

QN48

0.4

6 x 6

-

 

40(12)

40(9)

40(12)

 

QN48H

0.4

6 x 6

-

 

30(8)

-

-

H

QN48F

0.4

6 x 6

-

 

-

-

39(11)

F

QN48X

0.5

7 x 7

-

39(10)

-

-

-

X

CM64

0.5

4.1 x 4.1

-

 

 

-

55(16)

 

CS72

0.4

3.6 x 3.3

     

57(19)

-

 

CS81M

0.4

4.1 x 4.1

-

 

 

-

55(15)

M

QN88

0.4

10 x 10

-

-

57(17)

70(11)

70(19)

 

CS100H

0.4

4 x 4

-

-

88 (27)

-

-

H

LQ100

0.5

14 x 14

-

80(16)

80(15)

79(13)

79(20)

 

LQ100X

0.5

14 x 14

-

80(16)

80(15)

-

-

X

LQ144

0.5

20 x 20

-

-

113(28)

119(22)

120(28)

 

LQ144X

0.5

 

20 x 20

 

-

-

113(28)

-

-

X

LQ144F

0.5

20 x 20

-

-

115 (27)

-

-

F

EQ144

0.5

20 x 20

-

-

-

-

120(28)

 

MG49

0.5

3.8 x 3.8

-

-

42(11)

-

-

 

MG100

0.5

5 x 5

-

 -

-

-

87(25)

 

MG100T

0.5

5 x 5

-

-

-

-

87(17)

T

MG121

0.5

6 x 6

-

-

100(28)

-

-

 

MG121X

0.5

6 x 6

-

-

100(28)

-

-

X

MG132

0.5

8 x 8

-

-

104(29)

-

-

 

MG132H

0.5

8 x 8

-

-

94(29)

-

-

H

MG132X

0.5

8 x 8

-

-

104(29)

105(23)

-

X

MG160

0.5

8 x 8

-

-

-

131 (25)

131(38)

 

UG169

0.8

11 x 11

 

-

-

 

-

 129 (27)

129(38)

 

UG169

0.8

11 x 11

-

-

-

130 (27)

-

M

LQ176

0.4

20 x 20

-

-

-

-

147(37)

 

EQ176

0.4

20 x 20

-

-

-

-

147(37)

 

MG196

0.5

8 x 8

-

 -

-

-

113(35)

 

PG256

1.0

17 x 17

-

-

-

207(32)

207(36)

 

PG256M

1.0

17 x 17

-

-

-

207(32)

-

M

UG256

0.8

14 x 14

-

-

-

-

207(36)

 

UG332

0.8

17 x 17

-

-

-

-

273(43)

 

GW1N-1S

 

Note!

  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one. See UG103, GW1N series of FPGA Products Package and Pinout for further information
  • GW1N-1 CS30 only supportS SSPI mode
  • GW1N-1P5 & GW1N-2 device: When Mode[2:0] = I2C (3'b100), the loading rate at which the bitstream is transferred from Flash to SRAM is fixed at 2.5MHz, this may extend the device configuration time
  • For GW1N-4/GW1N-9 UV version devices, if Vcc and Vccx share a pin in a package, the Vccx range (2.5V~3.3V) of GW1N-4/GW1N-9 will limit the Vcc range to 2.5 V~3.3V, in this case Vcc does not support 1.8V.

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

H 10Gbps MIPI D-PHY Hard Core (2.5Gbps/lane x4 data lanes+ Clock lane)
F MSPI Programming
T MG100T is pin compatible with the GW1NR-MG100PT

 

GW1NR Series Table

 

Device GW1NR-1 GW1NR-2 GW1NR-4 GW1NR-9
LUT4 1,152 2304 4,608 8,640
Flip-Flop (FF) 864 2304 3,456 6,480
ShadowSRAM SSRAM(bits) 0 0 0 17,280
Block SRAM BSRAM(bits) 72K 72K 180K 468K
Number of BSRAM 4 4 10 26
User Flash (bits) 96K 96K 256K 608K
SDR SDRAM(bits) - - 64M 64M
Embedded PSRAM(bits) - 32-64M 32-64M 64-128M
NOR FLASH (bits) 4M 4M - -
18 x 18 Multiplier 0 0 16 20
PLLs 1 1 2 2
I/O Bank Number 4 7 4 4
Max. User I/O 120 126 218 276
Core Voltage (LV) 1.2V 1.2V 1.2V 1.2V
Core Voltage (UV) - 1.8V/2.5V/3.3V 2.5V/3.3V -


 


 

Package Options, Availible User I/O, (and LVDS Pairs):

  

Package Pitch(mm) Size(mm) GW1NR-1 GW1NR-2 GW1NR-4 GW1NR-9 Identifier
QN88 0.4 10 x 10 - - 70(11) 70(19)  
QN88P 0.4 10 x 10  - - 70(11) 70(17) P
MG49P 0.5 3.8 x 3.8 - 30(8) - - P
MG49PG 0.5 3.8 x 3.8 - 30(8) - - PG
MG49G 0.5 3.8 x 3.8 - 30(8) - - G
MG81P 0.5 4.5 x 4.5 - - 68(10) - P
MG100P 0.5 5 x 5  - - - 87(16) P
MG100PF 0.5 5 x 5 - - - 87(16) PF
MG100PA 0.5 5 x 5 - - - 87(17) PA
MG100PT 0.5 5 x 5 - - - 87(17) PT
MG100PS 0.5 5 x 5 - - - 87(17) PS
LQ144P 0.5 20 x 20  - - - 120(20) P
EQ144G 0.5 20 x 20  112 - - - G
LQ100G 0.5 14 x 14 75 - - - G
FN32G 0.4 4 x 4 26 - - - G
QN32X 0.5 5 x 5 26 - - - X
QN48X 0.5 7 x 7 41 - - - X

 


 

Package and Memory Information

 

Package Device Memory Capacity GW1NR-9 Identifier

QN88

GW1NR-4

SDR SDRAM

64M

16 bits

 

GW1NR-9

SDR SDRAM

64M

16 bits

 

QN88P

GW1NR-4

PSRAM

32M

8 bits

P

GW1NR-9

PSRAM

64M

16 bits

P

MG81P

GW1NR-4

PSRAM

64M

16 bits

P

MG100P

GW1NR-9

PSRAM

128M

32 bits

P

MG100PF

GW1NR-9

PSRAM

128M

32 bits

PF

MG100PA

GW1NR-9

PSRAM

128M

32 bits

PA

MG100PT

GW1NR-9

PSRAM

64M

16 bits

PT

MG100PS

GW1NR-9

PSRAM

64M

16 bits

PS

LQ144P

GW1NR-9

PSRAM

64M

16 bits

P

FN32G

LQ100G

EQ144G

QN32X

QN48X

 

GW1NR-1

NOR FLASH

4M

1 bit

G

MG49P

GW1NR-2

PSRAM

64M

16 bits

P

MG49G

GW1NR-2

NOR FLASH

4M

1 bit

G

MG49PG

GW1NR-2

PSRAM

32M (PSRAM)

8 bits

PG

NOR FLASH

4M (NOR FLASH)

1 bit

PG

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

P PSRAM
PG PSRAM, Alternative Pinout
G Alternative Pinout
PF PSRAM, MSPI Programming
PA AP memory PSRAM
PT Two PSRAM, compatible with GW1NR-LV9MG100P
PS Second PSRAM, compatible with GW1NR-LV9MG100PF

 


 

The GW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

 

Features:

  • Embedded 64 Mb pSRAM
  • Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
  • Small package sizes
  • Low power consumption
  • Dual Boot FPGA
  • Remote upgradeable bitstream

 

 

GW1NS Series Table

 

Parameter GW1NS-4 GW1NS-4C
LUT4 4,608 4,608
FF 3,456 3,456
B-SRAM bits 180K 180K
B-SRAM quantity 10 10
18 x 18 Multiplier 16 16
S-SRAM bits - -
User Flash bits 256K 256K
PLLs 2 2
OSC 1,+/-5% accuracy  1,+/-5% accuracy 
Hard Core Processor - Cortex-M3
I/O Banks 4 4
Max. User I/O 106 106
Core Voltage 1.2V 1.2V

 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package Pitch(mm) Size(mm) GW1NS-4 GW1NS-4C
CS49 0.4 2.9 x 2.9 42(8) 42(8)
MG64 0.5 4.2 x 4.2 57(8) 57(8)
QN48 0.4 6 x 6 38(4) 38(4)

 


The GW1NS FPGA SoC device inherits the innovation of LittleBee™ family with embedded ARM Cortex-M3 hardcore processor and integrated USB2.0 PHY, user flash, SRAM read/write controller and ADC convertor, providing customers all-in-one embedded solution with programable logic features in one chip. With Gowin integrated development environment, engineers can develop their hardware and software in a single platform, which is another innovation of FPGA design platform and reduces engineering design cycle.


 

Embedded 32-bit RISC Microprocessor

  • Arm Cortex-M3 (60 MHz)
  • 128K User Flash

 

Flash Configuration

  • Supports 2 image files
  • Supports Dual Boot
  • Online Upgradeable
  • Remote Upgrade

 

Integrated Development Flow for both M3 Core and FPGA Programming

  • Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

 

Fixed MIPI D-PHY I/O

  • I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

 

GW1NSR Version includes:

  • 32M-bits of embedded pSRAM memory
  • 8-bit wide, 332Mbps data rates (166 MHz clock)

 

Real-Time Operating Systems Supported

  • uCOSIII
  • FreeRTOS

 

GW1NS Video Training

Click Here

 

GW1NSE Secure FPGA Table

 

Parameter GW1NS-4C
LUT4 4,608
FF 3,456
B-SRAM bits 180K
B-SRAM quantity 10
18 x 18 Multiplier 16
S-SRAM bits -
User Flash bits 256K
PLLs 2
OSC 1,+/-5% accuracy 
Hard Core Processor Cortex-M3
I/O Banks 3
Max. User I/O 106
Core Voltage 1.2V

 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package

Pitch(mm) Size(mm) GW1NSE-4C GW1NSER-4C Identifier
QN48 0.4 6 x 6 - -  
LQ144 0.5 20 x 20 - -  
QN48P 0.4 6 x 6 - 38(4) P
QN48G 0.4 6 x 6 - 38(4) G

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

P PSRAM
G Alternative Pinout

 


 

GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device.  This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.

GW1NRF Series Table

 

Device GW1NRF-LV4B
LUT4 4,606
Flip-Flop (FF) 3,456
Shadow SRAM SSRAM (bits) 0
Block SRAM BSRAM (bits) 180K
Number of BSRAM 10
User Flash (bits) 256K
18 x 18 Multiplier 16
PLLs 2
I/O Bank Number 4
Max. User I/O 25
FPGA Core Voltage (LV) 1.2V
FPGA Core Voltage (UV) 1.8V/2.5V/3.3V
Bluetooth 5.0 LE RF Yes
32-bit ARC Processor Yes
Processor ROM (Bytes) 136K
Processor OTP (Bytes) 128K
Processor IRAM/DRAM (Bytes) 48K/28K
Security Core Yes
Power Management Unit Yes 
DCDC Step Up/Down Regulator Yes

 


 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package

Pitch (mm)

Size (mm) GW1NRF-LV4B
QN48 0.4 6 x 6 25(4)

 


The GW1NRF Bluetooth FPGA product features FPGA fabric, a power optimized 32-bit microprocessor, a power management unit capable of power as low as 5nA and a Bluetooth 5.0 Low Energy radio.  This extends the capabilities of Bluetooth devices by adding the flexible IO and heterogenous computing capabilities of the FPGA.

The GW1NRF BLE Module contains the GW1NRF-4 µSoC FPGA, radio antenna and appropriate passives.

 

Features

  • Integrated Bluetooth 5.0 Low Energy Radio
  • 4k LUT FPGA
  • 32-bit Power Optimized ARC Processor 

- 136kB ROM

- 128kB OTP for power efficiency

- 48kB IRAM and 28kB DRAM

  • Power Management Unit

-    5nA Chip Disable1 

-  < 1uA Sleep and Deep Disable1

-  < 5mA Processor + FPGA Active

  • Built-in DCDC Step Up/Down Regulator for Battery Operation
  • Hardened Security

- TRNG

- AES-128 Encryption Engine

  • ECC-P256 Key Generator
  • Module - International RF certifications available

 

Note!

  • [1]Does not include any leakage from external regulators when placed in standby

GW1NZ Series Table

 

Device GW1NZ-1
LUT4 1,152
Register 864
Shadow SRAM (bits) 4K
Block SRAM (bits) 72K
PLLs 1
User Flash (bits) 64K
Max. I/O 48
Core Voltage (LV)

1.2V

Core Voltage (ZV) 0.9V

  

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package

Pitch (mm)

Size (mm) GW1NZ-1 Identifier

QFN32

0.4

4 x 4

25

 

QFN32F

0.4

4 x 4

25

F

CS16

0.4

1.8 x 1.8

11

 

QFN48

0.4

6 x 6

40

 

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

F MSPI Programming

 


Note!

  • In this manual, abbreviations are employed to refer to the package types.
  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one.

Product Resources


 

Device GW1NZ-1 GW1N-2 GW1N-4
LUT4 1,152 2,304 4,604
Flip-Flop (FF) 864 2,304 3,456
Shadow SRAM Capacity (bits) 4K 0 0
Block SRAM Capacity (bits) 72K 72K 180K
Number of BSRAM - 4 10
User Flash (bits) 64K 96K 256K
18 x 18 Multiplier - 0 16
PLLs 1 1 2
Total Number of I/O banks - 7 4
Max. I/O 48 126 218
Core Voltage (LV) 1.2V 1.2V 1.2V
Core Voltage (UV) - - -
Core Voltage (ZV) - - -

 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package Pitch(mm) Size(mm) GW1NZ-1 GW1N-2 GW1N-4 Identifier
QN88 0.4 10 x 10 - - 70(11)  
QN88 0.4 10 x 10 - 58(17) - H
QN48 0.4 6 x 6 39 - -  

 

Note!

  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one. See UG103, GW1N series of FPGA Products Package and Pinout for further

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

H 10Gbps MIPI D-PHY Hard Core (2.5Gbps/lane x4 data lanes+ Clock lane)

 


 

GOWIN Semiconductor has been manufacturing automotive grade FPGA since early 2018. Providing fully certified AEC-Q100 Level-2 non-volatile Flash-based and SRAM FPGA devices that support a wide range of interface standards including MIPI-DPHY and LVDS.

GW1NSR Series Table

 

Parameter GW1NSR-4 GW1NSR-4C
LUT4 4,608 4,608
FF 3,456 3,456
B-SRAM bits 180K 180K
B-SRAM quantity 10 10
18 x 18 Multiplier 16 16
User Flash bits 256K 256K
HyperRAM(bits) - 64M
PSRAM(bits)
64M  64M
NOR FLASH(bits) - 32M
PLLs  2 2
OSC 1,+/- 5% accuracy 1,+/- 5% accuracy
Hard Core Processor - Cortex-M3
USB PHY - -
ADC Channels - -
I/O Banks 4 4
Max. User I/O 106 106
Core Voltage 1.2V 1.2V

 


  

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package

Pitch (mm)

Size (mm) GW1NSR-4 GW1NSR-4C Identifier
QN48P 0.4 6 x 6   39(4) P
QN48G 0.4 6 x 6   39(4) G
MG64P 0.5 4.2 x 4.2  55(8) 55(8) P

 


 

Package Identifier Defination Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

P PSRAM
G Alternative Pinout

 


The GW1NSR series of FPGA products are the first generation products in the LittleBee® family and represent one form of SIP chip.The main difference between the GW1NS series and the GW1NSR series is that the GW1NSR series integrates abundant PSRAM.