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PRODUCTS
Low Power, High Performance, High Reliability
Arora SRAM Based FPGAs

GOWIN’s Arora family of FPGA ICs offer a ‘best-in-class’ performance/cost ratio making it the ideal choice for compute intensive consumer, industrial, automotive and test equipment applications.

 

These mid-density SRAM based FPGAs offer optimized LUTs, DSPs, BSRAM, serialized I/O for real-time SoC, co-processing and signal processing development.

 

The Arora family is complemented by multiple innovative product line sub-features such as embedded PSRAM, DDR and Flash expanding its capabilities and usage compared to traditional FPGA products.

 

Arora FPGA Product Features:

 

  • Small Form Factor

-As small as 8x8mm2

  • High IO Count

-Up to 607 User IO

  • Serialized Interface Support

-MIPI CSI-2, MIPI DSI, LVDS, HDMI

-USB 2.0, PCI, Ethernet

-DDR3, HyperRAM, PSRAM

  • Extensive Pipeline Computing Resources

-Higher DSP Ratio

-Higher RAM Ratio

  • Flexible Programming Interface

-JTAG, MSPI, SSPI, I2C, CPU

-Multi-Boot

  • Embedded Security

-Bitstream Encryption

-Device Locking

  • Extension Features

-Integrated PSRAM and DDR3

-Integrated FLASH

-AEC-100Q Automotive Qualified

 

GW2A Series Table

 

Device GW2A-18 GW2A-55
LUT4 20,736 54,720
Flip-Flop (FF) 15,552 41,040
Shadow SRAM SSRAM(bits) 40K 106K
Block SRAM BSRAM(bits) 828K 2,520K
Number of BSRAM 46 140
18 x 18 Multiplier 48 40
PLLs 4 6
I/O Bank Number 8 8
Max. GPIOs 384 608
Core voltage Typ. 1.0V 1.0V

 


 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package Pitch (mm)

Size(mm)

E-pad size (mm) GW2A-18 GW2A-55 Identifier
QN88 0.4 10 x 10 6.74 x 6.74 66(22) -  
LQ144 0.5 20 x 20 119(34) -  
EQ144  0.5 20 x 20 9.74 x 9.74  119(34) -  
MG196 0.5 8 x 8 114(39)  
PG256 1.0 17 x 17 207(73) -  
PG256SF 1.0 17 x 17 192(71) SF
PG256C 1.0 17 x 17 190(64) C
PG256CF 1.0 17 x 17 190(65) CF
PG256E 1.0 17 x 17 - 162(29) - E
PG484 1.0 23 x 23 319(78) 319(76)  
PG484C 1.0 23 x 23 - 355(89) - C
PG1156 1.0 35 x 35 - 607(97)  
UG324 0.8 15 x 15 239(90) 239(86)  
UG324F 0.8 15 x 15 - - 239(86) F
UG324D 0.8 15 x 15 - - 239(71)

       D

UG484 0.8 19 x 19 - 379(94) -  
UG484S 0.8 19 x 19 - - 344(91) S
UG676 0.8 21 x 21 - - 525(97)  

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

F Complementary device with same pinout as S identifier; used as secondary device for use cases requiring daisy chain SPI programming
D UG324D offers alternative pinout supporting two DDR3 interfaces instead of one DDR3 interface on UG324. Using all A side IOs in the IO pair and DDR3 utilizes a 8:1 gear ratio. Allowing it to run up to 800Mb/s across all temperatures and voltages compared to other IOs using both A and B at a 4:1 ratio.

GW2AN Family Table

 

Device GW2AN-9X GW2AN-18X GW2AN-55

LUT4

10368

20,736

54,720

Flip-Flop (FF)

10368

15,552

41,040

SSRAM(bits)

40K

40K

106K

BSRAM(bits)

540K

540K

2,520K

BSRAM quantity

30

30

140

NOR Flash

16M bit

16M bit

32M

PLLs

2

2

6

Global Clock

8

8

-

High Speed Clock

8

8

-

LVDS (Mb/s)

1250

1250

-

MIPI (Mb/s)

1200

1200

-

Total number of I/O

banks

9

9

8

Max. GPIOs

389

389

608

Core voltage Typ. (LV)

1.0V

1.0V

1.0V

Core voltage Typ. (EV)

1.2V

1.2V

-

Core voltage Typ. (UV)

2.5V/3.3V

2.5V/3.3V

-

 


 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package Pitch (mm)

Size(mm)

GW2AN-9X GW2AN-18X GW2AN-55
Identifier

UG484

0.8

19 x 19

383(96)

383(96)

-

 

UG400

0.8

17 x 17

335(95)

335(95)

-

 

UG256

0.8

14 x 14

207(86)

207(86)

-

 

PG256

1.0

17 x 17

207(86)

207(86)

-

 

UG332

0.8

17 x 17

-

279(82)

-

 

UG324

0.8

15 x 15

279(74)

279(74)

-

 

PG484

1.0

23 x 23

381(96)

 

UG676

0.8

21x 21

525(97)

 

Note!

  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. For further detailed information, pelase refer toUG973, GW2AN series of FPGA Products Package and Pinout .

GW2AR Family Table

 

Device GW2AR-18
LUT4 20,736
Flip-Flop (FF) 15,552
Shadow SRAM SSRAM(bits) 40K
Block SRAM BSRAM(bits) 828K
Number of BSRAM  46
PSRAM (bits) 64M
SDR/DDR SDRAM (bits) 64M / 128M
18 x 18 Multiplier 48
PLLs 4
I/O Bank Number 8
Max. GPIOs 384
Core voltage Typ. 1.0V

 


 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package Pitch (mm) Size(mm) E-PAD Size (mm) GW2AR-18 Identifier
LQ144 0.5 20 x 20 - 120(35)  
EQ144 0.5 20 x 20 9.74 x 9.74 120(35)  
EQ144P 0.5 20 x 20 9.74 x 9.74 120(35) P
EQ144PF 0.5 20 x 20 9.74 x 9.74 120(35) PF
QN88 0.4 10 x 10 6.74 x 6.74 66(22)  
QN88P 0.4 10 x 10 6.74 x 6.74 66(22) P
QN88PF 0.4 10 x 10 6.74 x 6.74 66(22) PF
LQ176 0.4 20 x 20 -  140(45)  
EQ176 0.4 20 x 20 6 x 6 140(45)  

 


 

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

 

P PSRAM
PF PSRAM, MSPI Programming

GW2ANR Family Table

 

Device GW2ANR-18
LUT4 20,736
Flip-Flop (FF) 15,552
Shadow SRAM S-SRAM(bits) 40K
Block SRAM B-SRAM(bits) 828K
Number of B-SRAM 46
NOR FLASH (bits) 32M
SDR SDRAM (bits) 64M
18 x 18 Multiplier 48
PLLs 4
I/O Bank Number 8
Max. GPIOs 384
Core voltage Typ. 1.0V

 

Package Options, Availible User I/O, (and LVDS Pairs):

 

Package Device Memory Bit Width Capacity
PLL
QN88 GW2ANR-18 SDR SDRAM 32 bits 64M bits PLLL1/PLLR1
NOR FLASH 1 bit 32M bits

 


 

GW2ANR-18

Package Pitch(mm) Size(mm) E-PAD Size(mm) GW2AR-18
QN88 0.4 10 x 10 6.74 x 6.74 66(22)

 

GW2A-A Family Table

 

Parameter GW2A-LV18 A6
LUT4 20,736
Flip-Flop(FF) 15,552
Shadow SRAM Capacity(bits)
40K
Block SRAM (bits) 828K
User Flash(bits) -
18 x 18 Multiplier 48
PLLs 4
I/O banks 8
Core Voltage Typ. (LV) 1.0V

 

Package Options and Availible User I/O (LVDS Pairs):

 

Package Pitch (mm)

Size(mm)

E-pad

Size (mm)

GW2A-18

(Vehicle)

QN88 0.4 10 x 10 82(38) 66(22)
PG256 1 17 x 17 239(116) 207(73)

 

 

GOWIN Semiconductor has been manufacturing automotive grade FPGA since early 2018. Providing fully certified AEC-Q100 Level-2 non-volatile Flash-based and SRAM FPGA devices that support a wide range of interface standards including MIPI-DPHY and LVDS. 

 

GOWIN AEC-Q100 automotive qualified devices are ideally suited for interfacing and bridging camera sensors and displays for ADAS, 360o surround view, infotainment systems and LCD dashboard applications as well as system control, monitoring and management applications.

 

Over 10 complete solutions have been developed, many of which have passed vehicle   installation tests in a number of leading top automotive companies.