The GW1NZ series of FPGA products offer ultra-low power consumption, instant on, extreme low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer (especially mobile and wearable), etc.

Features

• Ultra low power consumption

－55nm embedded flash technology

－LV: Supports 1.2V core voltage

－ZV: Supports 0.9V core voltage (below 10uW standby power consumption with Power Management)

－Power Management Module

－Clock dynamically turns on and off

• Power Management Module

－SPMI: System power management interface hard core

• User Flash

－64K bits

－Data Width: 32

－ 10,000 write cycles

－Greater than ten years' data retention at +85 ℃

－Supports page erasure: 2048 bytes per page

－Duration: Max. 25ns

－Electric current

a) Read Operation: 2.19 mA/25 ns (V_CC) & 0.5 mA/25 ns (V_CCX) (MAX);

b) Write operation/erase operation: 12/12 mA(MAX)

－Quick page erasure/Write operation

－Clock frequency: 40MHz

－Write operation time: ≤16μs

－Page erasure time: ≤120 ms

• Multiple I/O Standards

－LVCMOS33/25/18/15/12；LVTTL33， PCI，

－LVDS25E，BLVDSE，MLVDSE，LVPECLE，RSDSE

－Input hysteresis option

－Supports 4mA,8mA,16mA,24mA,etc. drive options

－Slew Rate option

－Output drive strength option

－Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option

－Hot Socket

－I3C hard core, supports SDR mode

• Abundant Slices

－Four input LUT (LUT4)

－Double-edge flip-flops

－Supports shifter register

－Supports shadow SRAM

• Block SRAM with multiple modes

－Supports Dual Port, Single Port, and Semi Dual Port

－Supports bytes write enable

• Flexible PLLs

－Frequency adjustment (multiply and division) and phase adjustment

－Supports global clock

• Built-in Flash programming

－Instant-on

－Supports security bit operation

－Supports AUTO BOOT and DUAL BOOT

• Configuration

－JTAG configuration

－Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

GW1NZ Family Table

Package Information and Max. User I/O

GW1NS Video Training

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 GW1NS Family Table

Package Options with Max I/O (Refer to the latest datasheet for details)

Embedded 32-bit RISC Microprocessor

• Arm Cortex-M3 (60 MHz)
• 128K User Flash

Embedded ADC

• 8 Channels
• 12-bit SAR AD conversion
• 1 MHz Slew Rate
• Up to 16 MHz sampling clock

Flash Configuration

• Supports 2 image files
• Supports Dual Boot
• Online Upgradeable
• Remote Upgrade

Integrated Development Flow for both M3 Core and FPGA Programming

• Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

Embedded USB2.0 PHY

• 480 Mbps data speed
• Type-C compatible

Fixed MIPI D-PHY I/O

• I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

GW1NSR Version includes:

• 32M-bits of embedded pSRAM memory
• 8-bit wide, 332Mbps data rates (166 MHz clock)

Real-Time Operating Systems Supported

• uCOSIII
• FreeRTOS

The GW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

Features:

• Embedded 64 Mb pSRAM
• Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
• Small package sizes
• Low power consumption
• Dual Boot FPGA
• Remote upgradeable bitstream

GW1NR Family Table

Package Options and Max I/O (* Refer to the latest datasheet for details)

GW1N Family Table

Package Options and Max I/O (* Refer latest datasheet for details)

GW1N-1S

GW1N-1S

GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device.  This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.

Features:

• SRAM PUF (Physically Unclonable Function) Security
  • Root key pair generated based on intrinsic properties of internal device SRAM
  • Key pair generated at power up and never stored in the device
• Intrinsic ID BroadKey-Pro Security Library
  • Includes device identification, encryption and symmetric and asymmetric key generation
  • Example code for calling user functions
• Factory Provisioning
  • Device initialized with a key pair based on SRAM PUF
  • Private key never exposed during the manufacturing process
  • CSR and Certificate generated for each individual device
• Common User Applications
  • Secure Boot
  • Key and Signature Generation
  • Encryption/Decryption                 .

GW1NSE Secure FPGA Table