The GW1NZ series of FPGA products are the first generation products in the LittleBee^® family. They offer ultra-low power consumption, instant on, low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer, video control, etc.

GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1NZ series of FPGA products and applies to FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

Features

• Zero power consumption
  • 55nm embedded flash technology
  • LV: Supports 1.2V core voltage
  • ZV: Supports 0.9V core voltage. 
  • Clock dynamically turns on and off
  • User Falsh dynamically turns on and off

• Power Management Module(GW1NZ-1)

• • SPMI: System power management interface
  • VCC and VCCM are independent in the device

• User Flash(GW1NZ-1)
  • Dynamically turns on and off
  • 64K bits
  • Data Width: 32
  • 10,000 write cycles
  • Greater than ten years' data retention at +85 ℃
  • Supports page erasure: 2048 bytes per page
  • Duration: Max. 25ns
  • Electric current

• • 1. Read Operation: 2.19 mA/25 ns (V_CC) & 0.5 mA/25 ns (V_CCX) (MAX);
    2. Write operation/erase operation: 12/12 mA (MAX)
  • Quick page erasure/Write operation
  • Clock frequency: 40MHz
  • Write operation time: ≤16μs
  • Page erasure time: ≤120 ms

• User Flash (GW1NZ-2)
  • 10,000 write cycles
  • Greater than10 years Data Retention at +85 ℃
  • Data Width: 32
  • Capacity: 128 rows x 64 columns x 32 = 256kbits
  • Page Erase Capability: 2,048 bytes per page
  • Word Programming Time:≤16 μs
  • Page Erasure Time:≤120 ms

• Hard Core - MIPI D-PHY RX (GW1NZ-2)
  • Interfaces to MIPI CSI2 and DSI, RX devices
  • IO Bank1 supports MIPI D-PHY RX
  • MIPI transmission rate up to 5Gbps;
  • Supports up to 4 data lanes and one clock lane

• Soft Core - MIPI D-PHY RX/TX (GW1NZ-2)
  • Interfaces to MIPI CSI2 and DSI, RX and TX devices
  • IO Bank0, IO Bank3, IO Bank4, and IO Bank5 support MIPI D-PHY TX, and the transmission rate can be up to 1.5 Gbps
  • IO Bank1 and IO Bank2 support MIPI D-PHY RX, transmission speed can be up to 2Gbps

• Multiple I/O Standards

• • LVCMOS33/25/18/15/12；LVTTL33， PCI，
  • LVDS25E，BLVDSE，MLVDSE，LVPECLE，RSDSE
  • Input hysteresis option
  • Supports 4mA,8mA,16mA,24mA,etc. drive options
  • Slew Rate option
  • Output drive strength option
  • Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
  • Hot Socket
  • I3C hard core, supports SDR mode
  • Support differential output, rather than differential input

• Abundant Slices

• • Four input LUT (LUT4)
  • Double-edge flip-flops
  • Supports shifter register
  • Supports shadow SRAM

• Block SRAM with multiple modes

• • Supports Dual Port, Single Port, and Semi Dual Port
  • Supports bytes write enable

• Flexible PLLs

• • Frequency adjustment (multiplication and division) and phase adjustment
  • Supports global clock

• Built-in Flash programming

• • Instant-on
  • Supports security bit operation
  • Supports AUTO BOOT and DUAL BOOT

• Configuration

• • JTAG configuration
  • Offers up to seven GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I²C Slave

GW1NZ Family Table

Package Information and Max. User I/O

Note!

• In this manual, abbreviations are employed to refer to the package types.
• JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by

The GW1NSR series of FPGA products are the first generation products in the LittleBee® family and represent one form of SIP chip.The main difference between the GW1NS series and the GW1NSR series is that the GW1NSR series integrates abundant PSRAM. The GW1NSR series includes GW1NSR-2C and GW1NSR-2. ARM Cortex-M3 hard-core processor is embedded in the GW1NSR-2C device.

Features

• Lower power consumption
  - 55nm embedded flash technology
  - Core voltage: 1.2V
  - Support LX and UX
  - Clock dynamically turns on and off
• Integrate PSRAM system in package chip
• Hard core processor

- Cortex-M3 32-bit RISC

- ARM3v7M architecture optimized for small footprint embedded applications

• System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
  - Thumb compatible Thumb-2-only instruction set processor core for high code density
  - Up to 60 MHz operation
  - Hardware-division and single-cycle-multiplication
  - Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
  - 26 interrupts with eight priority levels
  - Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
  - Unaligned data access, enabling data to be efficiently packed into memory
  - Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
  - Timer0 and Timer1
  - UART0 and UART1
  - Watchdog
  - Debug port: JTAG and TPIU 
• USB2.0 PHY
  - 480Mbps data speed, compatible with USB1.1 1.5/12Mbps data speed
  - Plug and play
  - Hot socket
  
• ADC
  - Eight channels
  - 12-bit SAR AD conversion
  - Slew Rate: 1MHz
  - Dynamic range: >81 dB SFDR，>62 db SINAD
  - Linear performance: INL
• User Flash
  - 1Mb storage space
  - 32-bit data width
  
• Multiple I/O Standards
  - LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
  - MLVDSE, LVPECLE, RSDSE
  - Input hysteresis option
  - Supports 4mA,8mA,16mA,24mA,etc. drive options
  - Slew Rate option
  - Output drive strength option
  - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
  - Hot Socket
  - BANK0 supports MIPI input
  - BANK2 supports MIPI output
  - BANK0 and BANK2 support I3C
• Abundant Slices
  - Four input LUT (LUT4)
  - Double-edge flip-flops
  - Supports shifter register
• Block SRAM with multiple modes
  - Supports Dual Port, Single Port, and Semi Dual Port
  - Supports bytes write enable
• Flexible PLLs
  - Frequency adjustment (multiply and division) and phase adjustment
  - Supports global clock
• Built-in Flash programming
  - Instant-on
  - Supports security bit operation
  - Supports AUTO BOOT and DUAL BOOT
• Configuration
  - JTAG configuration
  - Supports on-chip DUAL BOOT configuration mode
  - Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL

GW1NSR Family Table

Note!

• [1]Supports up to 8-channel ADC. For the details, please refer to Table 2-2 Package
  Information.
•  

Package Information and Max. User I/O

GW1NS Video Training

Click Here

 GW1NS Family Table

Package Options with Max I/O (Refer to the latest datasheet for details)

Embedded 32-bit RISC Microprocessor

• Arm Cortex-M3 (60 MHz)
• 128K User Flash

Embedded ADC

• 8 Channels
• 12-bit SAR AD conversion
• 1 MHz Slew Rate
• Up to 16 MHz sampling clock

Flash Configuration

• Supports 2 image files
• Supports Dual Boot
• Online Upgradeable
• Remote Upgrade

Integrated Development Flow for both M3 Core and FPGA Programming

• Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

Embedded USB2.0 PHY

• 480 Mbps data speed
• Type-C compatible

Fixed MIPI D-PHY I/O

• I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

GW1NSR Version includes:

• 32M-bits of embedded pSRAM memory
• 8-bit wide, 332Mbps data rates (166 MHz clock)

Real-Time Operating Systems Supported

• uCOSIII
• FreeRTOS

The GW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

Features:

• Embedded 64 Mb pSRAM
• Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
• Small package sizes
• Low power consumption
• Dual Boot FPGA
• Remote upgradeable bitstream

GW1NR Family Table

Package Options and Max I/O (* Refer to the latest datasheet for details)

Features

• User Flash (GW1N-1,GW1N-1S)
  • 100,000 write cycles
  • Greater than10 years data retention at +85 ℃
  • Selectable 8/16/32 bits data-in and data-out
  • Page size: 256 bytes
  • 3 μA standby current
  • Page write time: 8.2 ms
• User Flash (GW1N-2/4/9)
  • 10,000 write cycles
  • Greater than10 years Data Retention at +85 ℃
  • Data Width: 32
  • GW1N-2/4 capacity: 128 rows x 64 columns x 32 = 256kbits
  • GW1N-9 capacity: 304 rows x 64 columns x 32 = 608kbits
  • Page Erase Capability: 2,048 bytes per page
  • Word Programming Time:≤16 μs
  • Page Erasure Time:≤120 ms
• Lower power consumption
  • 55 nm embedded flash technology

• • LV¹: Supports 1.2 V core voltage
  • UV: Supports same power supply for V_CC/ V_CCO/ V_CCx

Note!

[1] GW1N-1S supports LV Version only.

• • Clock dynamically turns on and off

• Hard Core - MIPI D-PHY RX (GW1N-2)
  • Interfaces to MIPI CSI2 and DSI, RX devices
  • IO Bank1 supports MIPI D-PHY RX
  • MIPI transmission rate up to 5Gbps;
  • Supports up to 4 data lanes and one clock lane
• Soft Core - MIPI D-PHY RX/TX (GW1N-2)
  • Interfaces to MIPI CSI2 and DSI, RX and TX devices
  • IO Bank0, IO Bank3, IO Bank4, and IO Bank5 support MIPI D-PHY TX, and the transmission speed can be up to 1.5 Gbps
  • IO Bank1 and IO Bank2 support MIPI D-PHY RX, transmission rate can be up to 2Gbps
• Multiple I/O Standards
  • LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE

MLVDSE, LVPECLE, RSDSE

• • Input hysteresis option
  • Supports 4mA,8mA,16mA,24mA,etc. drive options
  • Slew rate option
  • Output drive strength option
  • Individual bus keeper, weak pull-up, weak pull-down, and open drain option
  • Hot socket
  • BANK0/BANK1 of GW1N-1S support MIPI I/O input, and MIPI transmission speed can be up to 2Gbps
  • I/Os in the Top layer of GW1N-9 devices support MIPI input, and MIPI transmission speed can be up to 2Gbps
  • I/Os in the Bottom layer of GW1N-9 devices support MIPI output, and MIPI transmission speed can be up to 2Gbps
  • I/Os in the Top layer and Bottom layer of GW1N-9 devices support I3C OpenDrain/PushPull conversion

• High performance DSP
  • High performance digital signal processing ability
  • Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
  • Multipliers cascading
  • Registers pipeline and bypass
  • Adaptive filtering through signal feedback
  • Supports barrel shifter

• Abundant slices
  • Four input LUT (LUT4)
  • Double-edge flip-flops
  • Supports shift register and distributed register
• Block SRAM with multiple modes
  • Supports dual port, single port, and semi-dual port
  • Supports bytes write enable
• Flexible PLLs
  • Frequency adjustment (multiply and division) and phase adjustment
  • Supports global clock
• Built-in flash programming
  • Instant-on
  • Supports security bit operation
  • Supports AUTO BOOT and DUAL BOOT
• Configuration
  • JTAG configuration
  • B version/ C version devices support JTAG transparent transmission
  • Offers up to seven GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I²C Slave

GW1N Family Table

Note!

[1] Only GW1N-1 in LQ100X package offers both LV and UV versions at present

[2] In GW1N-2 seires, the package in CS42 has seven IO banks.

Package Options and Max I/O (* Refer latest datasheet for details)

GW1N-1S

GW1N-1S

Note!

• JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one. See UG103, GW1N series of FPGA Products Package and Pinout for further
• The package types in this data sheet are written with abbreviations. See 1Part Name.
• “         ” denotes that the various device pins are compatible when the package types are the

The GW1NRF Bluetooth FPGA product features FPGA fabric, a power optimized 32-bit microprocessor, a power management unit capable of power as low as 5nA and a Bluetooth 5.0 Low Energy radio.  This extends the capabilities of Bluetooth devices by adding the flexible IO and heterogenous computing capabilities of the FPGA.

The GW1NRF BLE Module contains the GW1NRF-4 µSoC FPGA, radio antenna and appropriate passives.

Features

• Integrated Bluetooth 5.0 Low Energy Radio
• 4k LUT FPGA
• 32-bit Power Optimized ARC Processor 

- 136kB ROM

- 128kB OTP for power efficiency

- 48kB IRAM and 28kB DRAM

• Power Management Unit

-    5nA Chip Disable¹ 

-  < 1uA Sleep and Deep Disable1

-  < 5mA Processor + FPGA Active

• Built-in DCDC Step Up/Down Regulator for Battery Operation
• Hardened Security

- TRNG

- AES-128 Encryption Engine

• ECC-P256 Key Generator
• Module - International RF certifications available

Note!

• [1]Does not include any leakage from external regulators when placed in standby

Package Options and Max I/O (* Refer latest datasheet for details)

GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device.  This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.

Features:

• SRAM PUF (Physically Unclonable Function) Security
  • Root key pair generated based on intrinsic properties of internal device SRAM
  • Key pair generated at power up and never stored in the device
• Intrinsic ID BroadKey-Pro Security Library
  • Includes device identification, encryption and symmetric and asymmetric key generation
  • Example code for calling user functions
• Factory Provisioning
  • Device initialized with a key pair based on SRAM PUF
  • Private key never exposed during the manufacturing process
  • CSR and Certificate generated for each individual device
• Common User Applications
  • Secure Boot
  • Key and Signature Generation
  • Encryption/Decryption                 .

GW1NSE Secure FPGA Table

 Features 

• Lower power consumption
  - 55nm embedded flash technology
  - Core voltage: 1.2V
  - Supports LV
  - Clock dynamically turns on and off
•  Integrated with HyperRAM
•  Integrated with NOR FLASH
•  Hard core processor
  - Cortex-M3 32-bit RISC
• - ARM3v7M architecture optimized for small-footprint embedded applications
  - System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
  - Thumb compatible Thumb-2-only instruction set processor core for high code density
  - Supports up to 100 MHz operation
  - Hardware-division and single-cycle-multiplication
  - Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
  - 26 interrupts with eight priority levels
  - Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
  - Unaligned data access, enabling data to be efficiently packed into memory
  - Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
  - Timer0 and Timer1
  - UART0 and UART1
  - Watchdog
  - Debug port: JTAG and TPIU
•  Offers OTP Authentication Code
•  User Flash
  - 256Kb storage space
  - 32-bit data width
•  Multiple I/O Standards
  - LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
  - MLVDSE, LVPECLE, RSDSE
  - Input hysteresis option
  - Supports 4mA,8mA,16mA,24mA,etc. drive options
  - Slew Rate option
  - Output drive strength option
  - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
  - Hot Socket- Supports MIPI interface
  - supports I3C
•  Abundant Slices
  - Four input LUT (LUT4)
  - Double-edge flip-flops
  - Supports shifter register
•  Block SRAM with multiple modes
  - Supports Dual Port, Single Port, and Semi Dual Port
  - Supports bytes write enable
•  Flexible PLLs
  - Frequency adjustment (multiply and division) and phase adjustment
  - Supports global clock
•  Built-in Flash programming
  - Instant-on
  - Supports security bit operation
  - Supports AUTO BOOT and DUAL BOOT
•  Configuration
  - JTAG configuration
  - Supports on-chip DUAL BOOT configuration mode
  - Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL