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PRODUCTS
Low Power, High Performance, High Reliability
LittleBee ® FPGAs

 

 

  • Low Power Non-volatile FPGA
 
  • Best in class of Performance Cost Ratio
  • Small footprint
  • MIPI standard supported
  • Embedded pSRAM (GW1NR/1NSR only) 
 

 

Based on 55nm LP technology, LittleBee® family offers instant-on, non-volatile, low power, intensive I/O and small footprint FPGA (smallest as 2.4x2.3mm). The family is ideal for high-performance bridging application and the 
first FPGA that supports MIPI I3C and MIPI D-PHY standard in the industry. The LittleBee® family is also the first non-volatile FPGA with an embedded pSRAM in the industry, which further reduces the board space and enhances performance.

  • User Flash (GW1N-1)

- 100,000 write cycles

- Greater than10 years Data Retention at +85°C

- Selectable 8/16/32 bits data-in and data-out

- Page size: 256 Bytes

- 3μA standby current

- Page Write Time: 8.2ms

 

  • User Flash (GW1N-2/4/9)

- Up to 1,792Kbits

- 10,000 write cycles

 

  • Lower Power Consumption

- 55nm embedded flash technology

- LV: supports 1.2V core voltage

- UV: built-in linear regulator, supports1.8V, 2.5V, and 3.3V core voltage input

- Clock dynamically turning on/ turning off

 

  • Multiple I/O Standards

- LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE

- Input hysteresis option

- Supports 4mA,8mA,16mA,24mA,etc. drive options

- Slew Rate option

- Output drive strength option

- Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option

- Hot Socket

 

  • High Performance DSP

- High performance digital signal processing ability

- Supports 9 x 9,18 x 18,36 x 36bit multiplier and 54bit accumulator;

- Multipliers cascading

- Registers pipeline and bypass

- Adaptive filtering through signal feedback

- Supports barrel shifter

 

  • Abundant Slices

- 4 input LUT (LUT4)

- Double-edge flip-flops

- Supports shift register and distributed register

 

  • Block SRAM with Multiple Modes

- Supports Dual Port, Single Port, and Semi Dual Port

- Supports bytes write enable

 

  • Flexible PLLs

- Frequency adjustment (multiply and division) and phase adjustment

- Supports global clock

 

  • Built-in Flash Programming

-  Instant-on

-  Supports security bit operation

-  Supports AUTO BOOT and DUAL BOOT

 

  • Configuration

- JTAG configuration

- Up to 6 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

GOWIN Semiconductor has been manufacturing automotive grade FPGA since early 2018. Providing fully certified AEC-Q100 Level-2 non-volatile Flash-based and SRAM FPGA devices that support a wide range of interface standards including MIPI-DPHY and LVDS.

 

Devices
GOWIN AEC-Q100 automotive qualified devices are ideally suited for interfacing and bridging camera sensors and displays for ADAS, 360o surround view, infotainment systems and LCD dashboard applications as well as system control, monitoring and management applications.

 

IP

GOWIN provides a wide range of freely-licenced reference designs and IP cores that are readily accessible using the IP Core Generator provided in our free FPGA EDA Design Software.

 

Solutions

Over 10 complete solutions have been developed, many of which have passed vehicle installation tests in a number of leading top automotive companies.

Features

  • User Flash (GW1N-1,GW1N-1S)
    • 100,000 write cycles
    • Greater than10 years data retention at +85 ℃
    • Selectable 8/16/32 bits data-in and data-out
    • Page size: 256 bytes
    • 3 μA standby current
    • Page write time: 8.2 ms
  • User Flash (GW1N-1P5/2/4/9)
    • 10,000 write cycles
    • Greater than10 years Data Retention at +85 ℃
    • Data Width: 32
    • GW1N-1P5/2/4 capacity: 128 rows x 64 columns x 32 = 256K bits
    • GW1N-9 capacity: 304 rows x 64 columns x 32 = 608 K bits
    • Page Erase Capability: 2,048 bytes per page
    • Word Programming Time:≤16 μs
    • Page Erasure Time:≤120 ms
  • Lower power consumption
    • 55 nm embedded flash technology
    • LV[1]: Supports 1.2 V core voltage
    • UV: Supports same power supply for VCC/ VCCO/ VCCx

Note!

[1] GW1N-1S supports LV Version only.

    • Clock dynamically turns on and off
  • Hard Core - MIPI D-PHY RX (GW1N-2)
    • Interfaces to MIPI DSI, and MIPI CSI-2, RX devices
    • IO Bank6 in CS42 package supports MIPI D-PHY RX
    • MIPI transmission rate up to 2Gbps per lane, 8Gbps per D-PHY interface;
    • Supports up to 4 data lanes and one clock lane
  • Multi-function Highspeed FPGA IO - MIPI D-PHY RX/TX (GW1N-2)
    • Interfaces to MIPI CSI-2 and MIPI DSI, RX and TX devices
    • MIPI D-PHY TX with dynamic ODT supported on IO Bank0, IO
      Bank3, IO Bank4, and IO Bank5 support
    • MIPI D-PHY RX with dynamic ODT supported on IO Bank2
      • ELVDS, TLVDS, SLVS200, LVDS and MIPI D-PHY IO;
  • Multiple I/O Standards
    • LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I,
      SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI,
      LVDS25, RSDS, LVDS25E, BLVDSE
      MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew rate option
    • Output drive strength option
    • Individual bus keeper, weak pull-up, weak pull-down, and open drain option
    • Hot socket
    • BANK0/BANK1 of GW1N-1S support MIPI I/O input, and MIPI
      transmission speed can be up to 1.2Gbps
    • I/Os in the Top layer of GW1N-9 devices support MIPI input, and MIPI transmission speed can be up to 1.2Gbps
    • I/Os in the Bottom layer of GW1N-9 devices support MIPI output, and MIPI transmission speed can be up to 1.2Gbps
    • I/Os in the Top layer and Bottom layer of GW1N-9 devices support I3C OpenDrain/PushPull conversion
  • High performance DSP
    • High performance digital signal processing ability
    • Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
    • Multipliers cascading
    • Registers pipeline and bypass
    • Adaptive filtering through signal feedback
    • Supports barrel shifter
  • Abundant slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shift register and distributed register
  • Block SRAM with multiple modes
    • Supports dual port, single port, and semi-dual port
    • Supports bytes write enable
  • Flexible PLLs
    • Frequency adjustment (multiply and division) and phase adjustment
    • Supports global clock
  • Built-in flash programming
    • Instant-on
    • Supports security bit operation
    • Supports AUTO BOOT and DUAL BOOT
  • Configuration
    • JTAG configuration
    • B version/ C version devices support JTAG transparent transmission
    • Offers up to seven GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I2C Slave

 

GW1N Series Table

 

Device GW1N-1  GW1N-1P5 GW1N-2

GW1N-4

GW1N-9 GW1N-1S

LUT4

1,152

1584

2304

4,608

8,640

1,152

 Flip-Flop (FF)

 864

1584

2016

 3,456

 6,480

 864

Shadow SRAM Capacity (bits)

0

12,672

18,432

0

17,280

0

Block SRAM Capacity(bits)

72 K

72K

72K

180 K

468 K

72K

Number of BSRAM

4

4

4

10

26

4

User Flash (bits)

96 K

96K

96K

256K

608K

96K

18 x 18 Multiplier

0

0

0

16

20

0

PLLs

1

1

1

2

2

1

Total number of I/O banks

4

6

6[2]

4

4

3

Max. I/O

120

125

126

218

276

44

Core Voltage (LV)

1.2 V

1.2V

1.2V

1.2 V

1.2 V

1.2V

Core Voltage (UV)

1.8V/2.5V/

3.3V[1]

1.8V/2.5V/3.3V

2.5V/3.3V

 

Note!

[1] In GW1N-1 series, only package in LQ100X offers both UV and LV version, other
packages in GW1N-1 series only offer LV version at present

[2] In GW1N-2 seires, the package in CS42 has seven IO banks.


 

Package Options and Max I/O (* Refer latest datasheet for details)

 

Package Pitch (mm) Size (mm2) GW1N-1S GW1N-1 GW1N-1P5 GW1N-2 GW1N-4 GW1N-9

CS30

0.4

2.3 x 2.4

23

24

-

 

-

-

QN32

0.5

5 x 5

-

26

-

-

24(3)

-

FN32

0.4

4 x 4

25

-

 

 

-

-

CS42

0.4

2.4 x 2.9

-

-

 

24(7)

-

-

QN48

0.4

6 x 6

-

41

 

40(12)

40(9)

40(12)

QN48H

0.4

6 x 6

-

-

 

30(8)

-

-

QN48F

0.4

6 x 6

-

-

 

-

-

39(11)

CM64

0.5

4.1 x 4.1

-

-

 

 

-

55(16)[1]

CS72

0.4

3.6 x 3.3

-

     

57(19)

-

CS81M

0.4

4.1 x 4.1

-

-

 

 

-

55(15)

QN88

0.4

10 x 10

-

-

 

-

70(11)

70(19)

LQ100

0.5

14 x 14

-

79

80(16)

80(15)

79(13)

79(20)

LQ100X

0.5

14 x 14

-

-

80(15)

80(15)

-

-

LQ144

0.5

20 x 20

-

116

 

113(28)

119(22)

120(28)

LQ144X

0.5

20 x 20

-

-

 

113 (28)

-

-

EQ144

0.5

20 x 20

-

-

 

-

-

120(28)

MG100

0.5

5 x 5

-

-

 

-

-

87(25)

MG100T

0.5

5 x 5

 

 

 

 

 

87(17)

MG121

0.5

6 x 6

 

 

 

100(28)

 

 

MG121X

0.5

6 x 6

 

 

 

100(28)

 

 

MG132

0.5

8 x 8

-

-

 

104(29)

 

 

MG132H

0.5

8 x 8

-

-

 

94 (29)

 

-

MG132X

0.5

8 x 8

 

 

 

104(29)

105(23)

 

MG160

0.5

8 x 8

-

-

 

-

131(25)

131(38)

UG169

0.8

11 x 11

-

-

 

-

-

129(38)

LQ176

0.4

20 x 20

-

-

-

-

-

147(37)

EQ176

0.4

20 x 20

-

-

-

-

-

147(37)

MG196

0.5

8 x 8

-

-

-

-

-

113(35)

PG256

1.0

17 x 17

-

-

-

-

207(32)

207(36)

PG256M

1.0

17 x 17

-

-

-

-

207(32)

-

UG256

0.8

14 x 14

-

-

-

-

-

207(36)

UG332

0.8

17 x 17

-

-

-

-

-

273(43)

GW1N-1S

GW1N-1S

Note!

  • [1] CM64 is only available in LV version but not UV version for GW1N-9 series
  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one. See UG103, GW1N series of FPGA Products Package and Pinout for further
  •          ” denotes that the various device pins are compatible when the package types are the same.

Introduction

The GW1N series of FPGA products are the first generation products in the LittleBee® family. They offer abundant logic resources, multiple I/O standards, embedded BSRAM, DSP, PLL, and built-in Flash. They are non-volatile FPGA products with low power, instant-start, low-cost,

high-security, small size, various packages, and flexible usage.

GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1N series of FPGA products and applies to FPGA synthesizing, placement and routing, data bitstream generation and download, etc.

Features

  • User Flash (GW1N-4)
    • 10,000 write cycles
    • Greater than10 years Data Retention at +85℃
    • Data Width: 32
    • Capacity: 128 rows x 64 columns x 32 = 256kbits
    • Page Erase Capability: 2,048 bytes per page
    • Word Programming Time:≤16 μs
    • Page Erasure Time:≤120 ms
  • Lower power consumption
    • 55 nm embedded flash technology
    • LV: Supports 2 V core voltage
    • UV: Supports same power supply for VCC/ VCCO/ VCCx
    • Clock dynamically turns on and off
  • Multiple I/O Standards
    • LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option

 

    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew rate option
    • Output drive strength option
    • Individual bus keeper, weak pull-up, weak pull-down, and open drain option
    • Hot socket
  • High performance DSP
    • High performance digital signal processing ability
    • Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
    • Multipliers cascading
    • Registers pipeline and bypass
    • Adaptive filtering through signal feedback
    • Supports barrel shifter
  • Abundant slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shift register and distributed register
  • Block SRAM with multiple modes
    • Supports dual port, single port, and semi-dual port
    • Supports bytes write enable
  • Flexible PLLs
    • Frequency adjustment (multiply and division) and phase adjustment
    • Supports global clock
  • Built-in flash programming
    • Instant-on
    • Supports security bit operation
    • Supports AUTO BOOT and DUAL BOOT
  • Configuration
    • JTAG configuration
    • B version/ C version devices support JTAG transparent transmission
    • Offers up to seven GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I2C Slave

 

Product Resources

Device GW1N-4

LUT4

4,608

Flip-Flop (FF)

3,456

Shadow SRAM Capacity (bits)

0

Block SRAM Capacity(bits)

180 K

Number of BSRAM

10

User Flash (bits)

256 K

18 x 18 Multiplier

16

PLLs

2

Total number of I/O banks

4

Max. I/O

218

Core Voltage (LV)

1.2 V

Core Voltage (UV)

2.5V/3.3V

 

Package Information

Package Pitch (mm) Size (mm) GW1N-4

QN88

0.4

10 x 10

70 (11)

PG256

1.0

17 x 17

207(32)

 

Note!

  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one. See UG103, GW1N series of FPGA Products Package and Pinout for further
  • The package types in this data sheet are written with abbreviations. See 1Part Name.

The GW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

 

Features:

  • Embedded 64 Mb pSRAM
  • Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
  • Small package sizes
  • Low power consumption
  • Dual Boot FPGA
  • Remote upgradeable bitstream

 


 

GW1NR Series Table

 

Device GW1NR-1 GW1NR-2 GW1NR-4 GW1NR-9
LUT4 1,152

2304

4,608 8,640
Flip-Flop (FF) 864

2304

(FF+Latch, FF:2016)

3,456 6,480
ShadowSRAM SSRAM(bits) 0 0 0 17,280
Block SRAM BSRAM(bits) 72K 72K 180K 468K
Number of B-SRAM  4 4 10 26
User Flash (bits) 96K 256K 256K 608K
SDR SDRAM(bits) - - 64M 64M
Embedded pSRAM(bits) -

64M(MG49P)

32M(MG49PG)

32M(QN88P)

64M(MG81P)

64M(QN88P/LQ144P/

MG100PT/MG100PS)
128M(MG100P/MG100PF

/MG100PA)

NOR FLASH (bits) 4M

4M(MG49G/MG49PG)

-

-

18 x 18 Multiplier 0

0

16 20
PLLs 1 1 2 2
I/O Bank Number 4 7 4 4
Max. User I/O 120 126 218 276
Core Voltage (LV) 1.2V 1.2V 1.2V 1.2V
Core Voltage (UV) - 1.8V/2.5V/3.3V 2.5V/3.3V

 


 



Package Options and Max I/O (* Refer to the latest datasheet for details)

  

Package Pitch (mm) Size (mm) GW1NR-1 GW1NR-2 GW1NR-4
 GW1NR-9
QN88 0.4 10 x 10

-

-

70(11)

70(19)

QN88P 0.4 10 x 10

-

-

70(11)

70(17)

MG49P 0.5 3.8 x 3.8

-

30(8)

-

-

MG49PG 0.5 3.8 x 3.8

-

30(8)

-

-

MG49G 0.5 3.8 x 3.8

-

30(8)

-

-

MG81P 0.5 4.5 x 4.5

-

-

68(10)

-

MG100P 0.5 5 x 5

-

-

-

87(16)

MG100PF 0.5 5 x 5

-

-

-

87(16)

MG100PA 0.5 5 x 5

-

-

-

87(17)

MG100PT 0.5 5 x 5

-

-

-

87(17)

MG100PS 0.5 5 x 5

-

-

-

87(17)

LQ144P 0.5 20 x 20 - - - 120(20)
FN32G 0.4 4 x 4 26 - - -

 

The GW1NRF Bluetooth FPGA product features FPGA fabric, a power optimized 32-bit microprocessor, a power management unit capable of power as low as 5nA and a Bluetooth 5.0 Low Energy radio.  This extends the capabilities of Bluetooth devices by adding the flexible IO and heterogenous computing capabilities of the FPGA.

The GW1NRF BLE Module contains the GW1NRF-4 µSoC FPGA, radio antenna and appropriate passives.

Features

  • Integrated Bluetooth 5.0 Low Energy Radio
  • 4k LUT FPGA
  • 32-bit Power Optimized ARC Processor 

- 136kB ROM

- 128kB OTP for power efficiency

- 48kB IRAM and 28kB DRAM

  • Power Management Unit

-    5nA Chip Disable1 

-  < 1uA Sleep and Deep Disable1

-  < 5mA Processor + FPGA Active

  • Built-in DCDC Step Up/Down Regulator for Battery Operation
  • Hardened Security

- TRNG

- AES-128 Encryption Engine

  • ECC-P256 Key Generator
  • Module - International RF certifications available

 

Note!

  • [1]Does not include any leakage from external regulators when placed in standby
Device

GW1NRF-LV4B

LUT4 4,606
Flip-Flop (FF) 3,456
Shadow SRAM SSRAM(bits) 0
Block SRAM BSRAM(bits) 180K
Number of BSRAM  10
User Flash (bits) 256K
18 x 18 Multiplier 16
PLLs 2
I/O Bank Number 4
Max. User I/O 25
FPGA Core Voltage (LV) 1.2V
FPGA Core Voltage (UV) 1.8v/2.5V/3.3V
Bluetooth 5.0 LE RF
Yes
32-bit ARC Processor
Yes
Processor ROM (Bytes)
136K
Processor OTP (Bytes)
128K
Processor IRAM/DRAM (Bytes)
48K/28K
Security Core
Yes
Power Management Unit
Yes
DCDC Step Up/Down Regulator Yes

 

Package Options and Max I/O (* Refer latest datasheet for details)

 

Package

Pitch (mm)

Size (mm) GW1NRF-LV4B
QFN48 0.4 6 x 6 25(4)

 

 

GW1NS Video Training

Click Here

 

 


 

 GW1NS Series Table

 

Parameter GW1NS-4 GW1NS-4C
LUT4 4,608 4,608
FF 3,456 3,456
B-SRAM bits 180K 180K
B-SRAM quantity 10 10
18 X 18 Multiplier 16 16
S-SRAM bits - -
User Flash bits 256K 256K
PLLs  2 2
OSC 1,+/- 5% accuracy 1,+/- 5% accuracy
Hard Core Processor - Cortex-M3
I/O Banks 4 4
Max. User I/O 106 106
Core Voltage 1.2V 1.2V

 


 

Package Options with Max I/O (Refer to the latest datasheet for details)

 

Package Pitch(mm) Size(mm) GW1NS-4 GW1NS-4C
CS36 0.4 2.5 x 2.5 - -
CS49 0.4 2.9 x 2.9 42(8) 42(8)
MG64 0.5 4.2 x 4.2 57(8) 57(8)
QN32 0.5 5 x 5 - -
QN32U 0.5 5 x 5 - -
QN48 0.4 6 x 6 38(4) 38(4)
LQ144 0.5 20 x 20 - -

 


 

Embedded 32-bit RISC Microprocessor

  • Arm Cortex-M3 (60 MHz)
  • 128K User Flash

 

Flash Configuration

  • Supports 2 image files
  • Supports Dual Boot
  • Online Upgradeable
  • Remote Upgrade

 

Integrated Development Flow for both M3 Core and FPGA Programming

  • Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

 

Fixed MIPI D-PHY I/O

  • I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

 

GW1NSR Version includes:

  • 32M-bits of embedded pSRAM memory
  • 8-bit wide, 332Mbps data rates (166 MHz clock)

 

Real-Time Operating Systems Supported

  • uCOSIII
  • FreeRTOS

GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device.  This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.

 

 

Features:

  • SRAM PUF (Physically Unclonable Function) Security
    • Root key pair generated based on intrinsic properties of internal device SRAM
    • Key pair generated at power up and never stored in the device
  • Intrinsic ID BroadKey-Pro Security Library
    • Includes device identification, encryption and symmetric and asymmetric key generation
    • Example code for calling user functions
  • Factory Provisioning
    • Device initialized with a key pair based on SRAM PUF
    • Private key never exposed during the manufacturing process
    • CSR and Certificate generated for each individual device
  • Common User Applications
    • Secure Boot
    • Key and Signature Generation
    • Encryption/Decryption                 .

 

GW1NSE Secure FPGA Table

Parameter

GW1NSE-4C

LUT4

4608

FF

3456

BSRAM (bits)

180K

BSRAM (#)

10

SSRAM (bits)

0

User Flash (Kbits)

256

18X18 Multiplier

16

PLLs 

2

OSC

1, +/- 5% accuracy

Hard Core Processor

Cortex-M3

USB 2.0 PHY

0

ADC Channels

0

I/O Banks

3

Max. User I/O

106

Core Voltage

1.2V

 

Package

Pitch(mm)

Size(mm)

 

GW1NSE-4C

 

QN48

0.4

6 x 6

-

LQ144

0.5

20 x 20

-

 

 

 Features 

  • Lower power consumption
    - 55nm embedded flash technology
    - Core voltage: 1.2V
    - Supports LV
    - Clock dynamically turns on and off
  •  Integrated with HyperRAM
  •  Integrated with NOR FLASH
  •  Hard core processor
    - Cortex-M3 32-bit RISC
  • - ARM3v7M architecture optimized for small-footprint embedded applications
    - System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
    - Thumb compatible Thumb-2-only instruction set processor core for high code density
    - Supports up to 100 MHz operation
    - Hardware-division and single-cycle-multiplication
    - Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
    - 26 interrupts with eight priority levels
    - Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
    - Unaligned data access, enabling data to be efficiently packed into memory
    - Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
    - Timer0 and Timer1
    - UART0 and UART1
    - Watchdog
    - Debug port: JTAG and TPIU
  •  Offers OTP Authentication Code
  •  User Flash
    - 256Kb storage space
    - 32-bit data width
  •  Multiple I/O Standards
    - LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
    - MLVDSE, LVPECLE, RSDSE
    - Input hysteresis option
    - Supports 4mA,8mA,16mA,24mA,etc. drive options
    - Slew Rate option
    - Output drive strength option
    - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    - Hot Socket- Supports MIPI interface
    - supports I3C
  •  Abundant Slices
    - Four input LUT (LUT4)
    - Double-edge flip-flops
    - Supports shifter register
  •  Block SRAM with multiple modes
    - Supports Dual Port, Single Port, and Semi Dual Port
    - Supports bytes write enable
  •  Flexible PLLs
    - Frequency adjustment (multiply and division) and phase adjustment
    - Supports global clock
  •  Built-in Flash programming
    - Instant-on
    - Supports security bit operation
    - Supports AUTO BOOT and DUAL BOOT
  •  Configuration
    - JTAG configuration
    - Supports on-chip DUAL BOOT configuration mode
    - Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL

 

 

Parameter GW1NSER-4C
LUT4 4,608
FF 3,456
BSRAM(bits) 180K
BSRAM(number) 10
18 x 18 Multiplier 16
User Flash(bits) 256K
HyperRAM(bits) 64M
NOR FLASH(Mbits) 32M
PLLs  2
OSC 1,+/- 5% accuracy
Hard Core Processor Cortex-M3
I/O Banks 4
Max. User I/O 106
Core Voltage 1.2V

 

 

Package

Pitch(mm)

Size(mm)

GW1NSER-4C

QN48P

0.4

6 x 6

38(4)

QN48G

0.4

6 x 6

38(4)

The GW1NSR series of FPGA products are the first generation products in the LittleBee® family and represent one form of SIP chip.The main difference between the GW1NS series and the GW1NSR series is that the GW1NSR series integrates abundant PSRAM. 

 

Features

  • Lower power consumption
    - 55nm embedded flash technology
    - Core voltage: 1.2V
    - Support LX and UX
    - Clock dynamically turns on and off
  • Integrate PSRAM system in package chip
  • Hard core processor

- Cortex-M3 32-bit RISC

- ARM3v7M architecture optimized for small footprint embedded applications

  • System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
    - Thumb compatible Thumb-2-only instruction set processor core for high code density
    - Up to 60 MHz operation
    - Hardware-division and single-cycle-multiplication
    - Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
    - 26 interrupts with eight priority levels
    - Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
    - Unaligned data access, enabling data to be efficiently packed into memory
    - Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
    - Timer0 and Timer1
    - UART0 and UART1
    - Watchdog
    - Debug port: JTAG and TPIU 
  • USB2.0 PHY
    - 480Mbps data speed, compatible with USB1.1 1.5/12Mbps data speed
    - Plug and play
    - Hot socket
  • ADC
    - Eight channels
    - 12-bit SAR AD conversion
    - Slew Rate: 1MHz
    - Dynamic range: >81 dB SFDR,>62 db SINAD
    - Linear performance: INL
  • User Flash
    - 1Mb storage space
    - 32-bit data width
  • Multiple I/O Standards
    - LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
    - MLVDSE, LVPECLE, RSDSE
    - Input hysteresis option
    - Supports 4mA,8mA,16mA,24mA,etc. drive options
    - Slew Rate option
    - Output drive strength option
    - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    - Hot Socket
    - BANK0 supports MIPI input
    - BANK2 supports MIPI output
    - BANK0 and BANK2 support I3C
  • Abundant Slices
    - Four input LUT (LUT4)
    - Double-edge flip-flops
    - Supports shifter register
  • Block SRAM with multiple modes
    - Supports Dual Port, Single Port, and Semi Dual Port
    - Supports bytes write enable
  • Flexible PLLs
    - Frequency adjustment (multiply and division) and phase adjustment
    - Supports global clock
  • Built-in Flash programming
    - Instant-on
    - Supports security bit operation
    - Supports AUTO BOOT and DUAL BOOT
  • Configuration
    - JTAG configuration
    - Supports on-chip DUAL BOOT configuration mode
    - Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL

 

GW1NSR Series Table

Parameter GW1NSR-4 GW1NSR-4C
LUT4 4,608 4,608
FF 3,456 3,456
B-SRAM bits 180K 180K
B-SRAM quantity 10 10
18 x 18 Multiplier 16 16
User Flash bits 256K 256K
HyperRAM(bits) - 64M
PSRAM(bits)
64M  64M
NOR FLASH(bits) - 32M
PLLs  2 2
OSC 1,+/- 5% accuracy 1,+/- 5% accuracy
Hard Core Processor - Cortex-M3
USB PHY - -
ADC Channels - -
I/O Banks 4 4
Max. User I/O 106 106
Core Voltage 1.2V 1.2V

 

Note!

  • [1]Supports up to 8-channel ADC. For the details, please refer to Table 2-2 Package
    Information.
  •  

  

Package Information and Max. User I/O

 

Package

Pitch (mm)

Size (mm) GW1NSR-4 GW1NSR-4C
QN48P 0.4 6 x 6   39(4)
QN48G 0.4 6 x 6   39(4)
MG64P 0.5 4.2 x 4.2  55(8) 55(8)

 

The GW1NZ series of FPGA products are the first generation products in the LittleBee® family. They offer ultra-low power consumption, instant on, low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer, video control, etc.

GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1NZ series of FPGA products and applies to FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

 

Features

 

  • Zero power consumption
    • 55nm embedded flash technology
    • LV: Supports 1.2V core voltage
    • ZV: Supports 0.9V core voltage.
    • Clock dynamically turns on and off
    • User Falsh dynamically turns on and off

 

  • Power Management Module(GW1NZ-1)
    • SPMI: System power management interface
    • VCC and VCCM are independent in the device

 

  • User Flash(GW1NZ-1)
    • Dynamically turns on and off
    • 64K bits
    • Data Width: 32
    • 10,000 write cycles
    • Greater than ten years' data retention at +85 ℃
    • Supports page erasure: 2048 bytes per page
    • Duration: Max. 25ns
    • Electric current
      1. Read Operation: 2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX);
      2. Write operation/erase operation: 12/12 mA (MAX)
    • Quick page erasure/Write operation
    • Clock frequency: 40MHz
    • Write operation time: ≤16μs
    • Page erasure time: ≤120 ms
  •  

 

  • Multiple I/O Standards
    • GW1NZ-1: LVCMOS33/25/18/15/12;LVTTL33; PCI;
      LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew Rate option
    • Output drive strength option
    • Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    • Hot Socket
    • I3C hard core, supports SDR mode
    • Support differential output, rather than differential input

 

  • Abundant Slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shifter register
    • Supports shadow SRAM

 

  • Block SRAM with multiple modes
    • Supports Dual Port, Single Port, and Semi Dual Port
    • Supports bytes write enable

 

  • Flexible PLLs
    • Frequency adjustment (multiplication and division) and phase adjustment
    • Supports global clock

 

  • Built-in Flash programming
    • Instant-on
    • Supports security bit operation
    • Supports AUTO BOOT and DUAL BOOT

 

  • Configuration
    • JTAG configuration
    • Offers up to seven GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

 


  

GW1NZ Series Table

 

Device GW1NZ-1

LUT4

1,152

Register

864

Shadow SRAM (bits)

4K

Block SRAM (bits)

72K

PLLs

1

User Flash (bits)

64K

Max. I/O

48

Core Voltage (LV)

1.2V

Core Voltage (ZV)

0.9V

 


  

Package Information and Max. User I/O

 

Package

Pitch (mm)

Size (mm) GW1NZ-1

FN32

0.4

4 x 4

25

FN32F

0.4

4 x 4

25

CS16

0.4

1.8 x 1.8

11

QN48

0.4

6 x 6

40

Note!

  • In this manual, abbreviations are employed to refer to the package types.
  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one.

Introduction
The GW1NZ series of FPGA products are the first generation products
in the LittleBee® family. They offer ultra-low power consumption, instant on,
low cost, non-volatile, high security, various packages, and flexible usage.
They can be widely used in communication, industry control, consumer,
video control, etc.
GOWINSEMI provides a new generation of FPGA hardware
development environment through market-oriented independent research
and development that supports the GW1NZ series of FPGA products and
applies to FPGA synthesizing, layout, place and routing, data bitstream
generation and download, etc.

Features

  • Zero power consumption
    • 55nm embedded flash technology
    • LV: Supports 2V core voltage
    • ZV: Supports 9V core voltage
    • Clock dynamically turns on and off
    • User Flash dynamically turns on and off
  • Power Management Module (GW1NZ-1)
    • SPMI: System power management interface
    • VCC and VCCM are independent in the device
  • User Flash (GW1NZ-1)
    • Dynamically turns on and off
    • 64K bits
    • Data Width: 32
    • 10,000 write cycles
    • Greater than ten years' data retention at +85 ℃
    • Supports page erasure: 2048 bytes per page
    • Duration: 25ns
    • Electric current
      • Read Operation: 2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX);
      • Write operation/erase operation: 12/12 mA (MAX)
    • Quick page erasure/Write operation
    • Clock frequency: 40MHz
    • Write operation time: ≤16μs
    • Page erasure time: ≤120 ms
  • Multiple I/O Standards
    • GW1NZ-1: LVCMOS33/25/18/15/12;LVTTL33; PCI; LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew Rate option
    • Output drive strength option
    • Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    • Hot Socket
    • I3C hard core, supports SDR mode
    • Support differential output, rather than differential input
  • Abundant Slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shifter register
    • Supports shadow SRAM
  • Block SRAM with multiple modes
    • Supports Dual Port, Single Port, and Semi Dual Port
    • Supports bytes write enable
  • Flexible PLLs
    • Frequency adjustment (multiplication and division) and phase adjustment
    • Supports global clock
  • Built-in Flash programming
    • Instant-on
    • Supports security bit operation
    • Supports AUTO BOOT and DUAL BOOT
  • Configuration
    • JTAG configuration
    • Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, and DUAL BOOT

 

Device GW1NZ-1

LUT4

1,152

Register

864

Shadow SRAM (bits)

4K

Block SRAM (bits)

72K

PLLs

1

User Flash (bits)

64K

Max. I/O

48

Core Voltage (LV)

1.2V

Core Voltage (ZV)

0.9V

 

Package Information

Package Pitch (mm) Size (mm) GW1NZ-1

FN32

0.4

4 x 4

25

FN32F

0.4

4 x 4

25

CS16

0.4

1.8 x 1.8

11

QN48

0.4

6 x 6

40

  •