The GW1NZ series of FPGA products offer ultra-low power consumption, instant on, extreme low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer (especially mobile and wearable), etc.

Features

• Ultra low power consumption

－55nm embedded flash technology

－LV: Supports 1.2V core voltage

－ZV: Supports 0.9V core voltage (below 10uW standby power consumption with Power Management)

－Power Management Module

－Clock dynamically turns on and off

• Power Management Module

－SPMI: System power management interface hard core

• User Flash

－64K bits

－Data Width: 32

－ 10,000 write cycles

－Greater than ten years' data retention at +85 ℃

－Supports page erasure: 2048 bytes per page

－Duration: Max. 25ns

－Electric current

a) Read Operation: 2.19 mA/25 ns (V_CC) & 0.5 mA/25 ns (V_CCX) (MAX);

b) Write operation/erase operation: 12/12 mA(MAX)

－Quick page erasure/Write operation

－Clock frequency: 40MHz

－Write operation time: ≤16μs

－Page erasure time: ≤120 ms

• Multiple I/O Standards

－LVCMOS33/25/18/15/12；LVTTL33， PCI，

－LVDS25E，BLVDSE，MLVDSE，LVPECLE，RSDSE

－Input hysteresis option

－Supports 4mA,8mA,16mA,24mA,etc. drive options

－Slew Rate option

－Output drive strength option

－Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option

－Hot Socket

－I3C hard core, supports SDR mode

• Abundant Slices

－Four input LUT (LUT4)

－Double-edge flip-flops

－Supports shifter register

－Supports shadow SRAM

• Block SRAM with multiple modes

－Supports Dual Port, Single Port, and Semi Dual Port

－Supports bytes write enable

• Flexible PLLs

－Frequency adjustment (multiply and division) and phase adjustment

－Supports global clock

• Built-in Flash programming

－Instant-on

－Supports security bit operation

－Supports AUTO BOOT and DUAL BOOT

• Configuration

－JTAG configuration

－Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

GW1NZ Family Table

Package Information and Max. User I/O

The GW1NSR series of FPGA products are the first generation products in the LittleBee® family and represent one form of SIP chip.The main difference between the GW1NS series and the GW1NSR series is that the GW1NSR series integrates abundant PSRAM. The GW1NSR series includes GW1NSR-2C and GW1NSR-2. ARM Cortex-M3 hard-core processor is embedded in the GW1NSR-2C device.

Features

• Lower power consumption
  - 55nm embedded flash technology
  - Core voltage: 1.2V
  - Support LX and UX
  - Clock dynamically turns on and off
• Integrate PSRAM system in package chip
• Hard core processor

- Cortex-M3 32-bit RISC

- ARM3v7M architecture optimized for small footprint embedded applications

• System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
  - Thumb compatible Thumb-2-only instruction set processor core for high code density
  - Up to 60 MHz operation
  - Hardware-division and single-cycle-multiplication
  - Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
  - 26 interrupts with eight priority levels
  - Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
  - Unaligned data access, enabling data to be efficiently packed into memory
  - Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
  - Timer0 and Timer1
  - UART0 and UART1
  - Watchdog
  - Debug port: JTAG and TPIU 
• USB2.0 PHY
  - 480Mbps data speed, compatible with USB1.1 1.5/12Mbps data speed
  - Plug and play
  - Hot socket
  
• ADC
  - Eight channels
  - 12-bit SAR AD conversion
  - Slew Rate: 1MHz
  - Dynamic range: >81 dB SFDR，>62 db SINAD
  - Linear performance: INL
• User Flash
  - 1Mb storage space
  - 32-bit data width
  
• Multiple I/O Standards
  - LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
  - MLVDSE, LVPECLE, RSDSE
  - Input hysteresis option
  - Supports 4mA,8mA,16mA,24mA,etc. drive options
  - Slew Rate option
  - Output drive strength option
  - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
  - Hot Socket
  - BANK0 supports MIPI input
  - BANK2 supports MIPI output
  - BANK0 and BANK2 support I3C
• Abundant Slices
  - Four input LUT (LUT4)
  - Double-edge flip-flops
  - Supports shifter register
• Block SRAM with multiple modes
  - Supports Dual Port, Single Port, and Semi Dual Port
  - Supports bytes write enable
• Flexible PLLs+DLLs
  - Frequency adjustment (multiply and division) and phase adjustment
  - Supports global clock
• Built-in Flash programming
  - Instant-on
  - Supports security bit operation
  - Supports AUTO BOOT and DUAL BOOT
• Configuration
  - JTAG configuration
  - Supports on-chip DUAL BOOT configuration mode
  - Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL

GW1NSR Family Table

Note!

• [1]Supports up to 8-channel ADC. For the details, please refer to Table 2-2 Package
  Information.

Package Information and Max. User I/O

GW1NS Video Training

Click Here

 GW1NS Family Table

Package Options with Max I/O (Refer to the latest datasheet for details)

Embedded 32-bit RISC Microprocessor

• Arm Cortex-M3 (60 MHz)
• 128K User Flash

Embedded ADC

• 8 Channels
• 12-bit SAR AD conversion
• 1 MHz Slew Rate
• Up to 16 MHz sampling clock

Flash Configuration

• Supports 2 image files
• Supports Dual Boot
• Online Upgradeable
• Remote Upgrade

Integrated Development Flow for both M3 Core and FPGA Programming

• Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

Embedded USB2.0 PHY

• 480 Mbps data speed
• Type-C compatible

Fixed MIPI D-PHY I/O

• I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

GW1NSR Version includes:

• 32M-bits of embedded pSRAM memory
• 8-bit wide, 332Mbps data rates (166 MHz clock)

Real-Time Operating Systems Supported

• uCOSIII
• FreeRTOS

The GW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

Features:

• Embedded 64 Mb pSRAM
• Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
• Small package sizes
• Low power consumption
• Dual Boot FPGA
• Remote upgradeable bitstream

GW1NR Family Table

Package Options and Max I/O (* Refer to the latest datasheet for details)

GW1N Family Table

Package Options and Max I/O (* Refer latest datasheet for details)

GW1N-1S

GW1N-1S

The GW1NRF Bluetooth FPGA product features FPGA fabric, a power optimized 32-bit microprocessor, a power management unit capable of power as low as 5nA and a Bluetooth 5.0 Low Energy radio.  This extends the capabilities of Bluetooth devices by adding the flexible IO and heterogenous computing capabilities of the FPGA.

Features

• Integrated Bluetooth 5.0 Low Energy Radio
• 4k LUT FPGA
• 32-bit Power Optimized ARC Processor 

- 136kB ROM

- 128kB OTP for power efficiency

- 48kB IRAM and 28kB DRAM

• Power Management Unit

-    5nA Chip Disable¹ 

-  < 1uA Sleep and Deep Disable1

-  < 5mA Processor + FPGA Active

• Built-in DCDC Step Up/Down Regulator for Battery Operation
• Hardened Security

- TRNG

- AES-128 Encryption Engine

- ECC-P256 Key Generator

Package Options and Max I/O (* Refer latest datasheet for details)

GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device.  This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.

Features:

• SRAM PUF (Physically Unclonable Function) Security
  • Root key pair generated based on intrinsic properties of internal device SRAM
  • Key pair generated at power up and never stored in the device
• Intrinsic ID BroadKey-Pro Security Library
  • Includes device identification, encryption and symmetric and asymmetric key generation
  • Example code for calling user functions
• Factory Provisioning
  • Device initialized with a key pair based on SRAM PUF
  • Private key never exposed during the manufacturing process
  • CSR and Certificate generated for each individual device
• Common User Applications
  • Secure Boot
  • Key and Signature Generation
  • Encryption/Decryption                 .

GW1NSE Secure FPGA Table