Evaluating GW5AT SerDes Channel Performance Across Various Transmission Media

1 Abstract

This white paper presents the performance evaluation of the GW5AT SerDes (Serializer/Deserializer) solution under different channel configurations and cable assemblies. The tests aim to assess the signal integrity and achievable data rates across a variety of interconnect media, including standard PCB, ISI boards, DisplayPort (DP) cables, HDMI cables, HSD cables, and fiber optics.

2 Introduction

As high-speed serial interfaces continue to evolve, ensuring robust data transmission across various physical channels becomes increasingly important. Testing GW5AT’s SerDes (Serializer/Deserializer) technology across different transport media—such as various types of cables (e.g., coaxial, twisted pair, optical fiber) is important for several critical reasons:

1. Signal Integrity Varies with Cable Type
   • Different cables introduce different types of signal degradation:
     • Attenuation (loss of signal strength)
     • Crosstalk (interference between channels)
     • Impedance mismatch and reflections
     • Dispersion (especially in fiber)
   • SerDes systems must maintain low bit error rates (BER) even under these degradations.

2. Cable Length and Material Affect Performance

• Longer cables increase latency and attenuation.
• Material differences (e.g., copper vs. fiber) affect signal speed, bandwidth, and electromagnetic interference (EMI).
• SerDes systems must be tested for maximum reach and data integrity across realistic distances.

3. Jitter and Timing Recovery Depend on Media

• Jitter tolerance (timing variation) is a key parameter in SerDes design.
• Different media introduce different jitter profiles, which impact clock and data recovery (CDR) circuits.

4. EMC/EMI Compliance and Robustness

• Cable shielding and construction affect electromagnetic compatibility.
• Testing ensures the SerDes link does not emit or succumb to unacceptable EMI, especially in industrial or automotive applications.

5. Application-Specific Reliability

• Applications (data center, automotive, aerospace) use different media due to environmental, cost, or legacy reasons.
• SerDes must be tested for real-world deployment scenarios:

e.g., harsh environments in automotive vs. controlled data center conditions.

6. Standard Compliance

• Industry standards (e.g., PCIe, Ethernet, JESD204B/C) specify performance over certain types of media.
• Testing across those media ensures compliance and interoperability.

7. Equalization and Adaptive Algorithms Tuning

• SerDes often use adaptive equalization to compensate for channel loss.
• Testing across different media helps tune these algorithms for best performance under various conditions.

In Summary, testing SerDes technology with different transport media is essential to validate performance, reliability, compliance, and interoperability. Without this, the system may fail or underperform in actual deployment environments.

3 Basic Terminologies

Let’s review some basic concepts and terminologies before going into the detailed discussion of the testing and results.

3.1 Channel Insertion Loss

Channel Insertion Loss is the loss of signal power that occurs as the signal travels through a transmission channel (such as a cable, PCB trace, connector, or backplane).

It tells you how much signal is lost between the transmitter and receiver at a given frequency.

Insertion Loss (IL) is the ratio (in dB) of the signal power at the input vs. the signal power at the output of a transmission path, often expressed as a function of frequency.

Formula:

Insertion loss is caused by a combination of:

Typical behavior with Frequency as follows

• Insertion loss increases with frequency.
• At high data rates (e.g., 10+ Gbps), even small lengths of PCB trace or cable can introduce significant attenuation.

Measured typically using a Vector Network Analyzer (VNA) or Time Domain Reflectometer (TDR). 

Here is an example of the Channel Insertion Loss curve, showing how signal loss increases with frequency. As you can see, higher frequencies (common in high-speed SerDes systems) experience significantly greater attenuation, which is why insertion loss is a critical parameter to evaluate and compensate for in system design.

In our actual test system, the total insertion loss represents the attenuation from the serializer SIO pin to the Deserializer SIO pin and includes several components. Each IL of components is measured as follows:

• Serializer PKG & PCB Trace: -2 dB
• Deserializer PKG & PCB Trace: -2 dB
• Cable Assembly Insertion Loss:
  • Cable A & C: -0.5 dB each
  • ISI Board or Cable B: varies by configuration

3.2 Emphasis Technology

Emphasis technology refers to signal conditioning techniques that shape the transmitted waveform by adjusting the amplitude of different signal parts, which are usually based on transition patterns, to counteract channel losses. It’s commonly used in high-speed serial links like PCIe, USB, Ethernet, SATA, etc., to maintain data integrity over lossy media (e.g., long cables, backplanes, PCB traces).

There are mainly two types of Emphasis technology. Both techniques boost high-frequency content (which tends to get attenuated more on real channels) but do so in different ways.

• Pre-Emphasis: Increases the amplitude of signal transitions (i.e., when the bit changes from 0→1 or 1→0)
• De-Emphasis: Decreases the amplitude of steady-state signals (i.e., when the bit stays the same over time)

3.3 PRBS Signals

A PRBS (Pseudo-Random Binary Sequence) is a deterministic, repeatable sequence of binary bits (0 and 1) that mimics the randomness of real-world data traffic but is generated using a known mathematical formula. It's called “pseudo-random” because the sequence appears random, but it’s generated by a fixed pattern from a shift register with feedback taps.

Common PRBS Patterns

PRBS is often used in Serdes testing for:

• Transmitter compliance testing (e.g., measuring eye diagram or jitter)
• Receiver sensitivity testing
• Loopback tests (internal or external)
• BER tests: PRBS is sent, then checked for mismatches at the receiver

3.4 BER Testing

BER (Bit Error Rate) is the ratio of the number of bit errors to the total number of bits transmitted during a test.

Example:

If 10 errors occur over 1,000,000,000 bits:

BER testing is the process of transmitting a known data pattern (like a PRBS sequence) through the communication channel and comparing the received data to the original. Any mismatches are counted as bit errors.

The goal of BER testing is as follows:

Here is a simulated BER vs. Time plot for a high-speed link test:

• The green curve shows how BER improves over time as the link stabilizes.
• The red dashed line marks a common industry target BER threshold of 1e-12.
• In a real test, this helps verify if the system meets reliability specs over time.

4 Test Setup

To ensure accurate cable measurement results, a series of carefully designed testing steps are followed. Since the test setup requires additional boards and cables to connect the cable under test, these supporting components must be measured first to account for their impact. The detailed setup of the test bench is described in the following sections.

4.1 Hardware Configuration

The first step is to measure the transmitter character with the tester and its probe cables. The following diagram shows the detailed setup.

Test Setup 1: TX Performance Observation

The transmitter board is EVAL_GW5AT_60KUG225_V1’s LN1 TX connector, and the receiver board is EVAL_GW5AT_60KUG225_V1’s LN1 RX connector.

Here is the actual picture of this setup:

Test Setup 1

The second step is to measure the ISI board characters as the following diagram:

Setup 2: ISI board connected to the Tx and Rx boards

The following shows the actual setup picture:

ISI board connections

The 3^rd step is to measure the actual target cable performance. The test bench was set up as described as follows:

Test Setup 3: Cable Assemblies

4.2 Common Test Parameters

Here are some common test parameters used in the tests we just described in the last section.

• Bit Error Rate (BER) Target: 1e-12
• Test Pattern: PRBS15
• TX De-emphasis: Varied (-1.94 dB to -6 dB)
• RX Equalization: AUTO
• Cable Lengths: Ranged from 0.3m to 10m, depending on media

4.3 Test Equipment

Here is the test equipment list we used in the tests we described previously:

• Oscilloscope: Keysight UXR0254A
• Network Analyzer: Keysight E5071C

4.4 Channel Insertion Loss

Here are the insertion loss represents the attenuation from the serializer SIO pin to the Deserializer SIO pin, and includes:

• Serializer PKG & PCB Trace: -2 dB
• Deserializer PKG & PCB Trace: -2 dB
• Cable Assembly Insertion Loss:
• Cable A & C: -0.5 dB each
• ISI Board or Cable B: varies by configuration
  
  

5 Test Results with Different Channels

5.1       TX Performance

The first test is to observe the transmitter characteristics. The following picture shows the test setup. The board that is used here is EVAL_GW5AT_60KUG225_V1. All the cables will be used in the following test steps.

Test setup for Transmit performance observation

The Eye Diagrams observed for different speeds are as follows:

Eye Diagram at 12.5Gbps

Eye Diagram at 10Gbps

5.2       FR4 ISI Board

The second test is to observe the ISI board‘s characteristics. The following picture shows the test setup. The board that is used here is the ISI board. All the cables will be used in the following test steps.

ISI board testing setup

Here are the channel loss measurement results for the 0.635-meter PCB trace and 0.3-meter PCB trace on the ISI board:

Channel loss measurement results

For speed testing, we monitor the internal Serdes data received through our proprietary FPGA testing channels. The failure point is indicated by the total collapse of the eye diagram.  The following internal eye diagram is for a 0.635m FR4 PCB trace, the signal is running at 9Gbps. The transmitter side De-emphasis is set at -6 dB.  

Internal Eye diagram

The following internal eye diagram is for a 0.3m FR4 PCB trace, the signal is running at 12Gbps. The transmitter side De-emphasis is set at -6 dB.  

Internal Eye diagram

5.3      DP 1.4 Cable Measurement

The following test is for a DisplayPort 1.4 cable. We chose this cable from the vendor samzheglobal.com. 30 American Wire Gauge (AWG). Cable length is 2 meters. The insertion loss is measured in the following picture:

Insertion loss for SAMZHE 30AWG DP cable

The test bench setup is shown in the following picture:

Test Setup for DP 1.4 cable measurement

The following internal eye diagram is for a 2m DisplayPort 1.4 cable, the signal is running at 11Gbps. The transmitter side De-emphasis is set at -3 dB.

                           Internal Eye diagram

5.4       HDMI 2.1 Cable

The following test is for an HDMI 2.1 cable. We chose this cable from vendor UGREEN. 32 AWG. Cable length is 2meters. The insertion loss is measured as the following picture:

Insertion loss for UGREEN 32AWG HDMI cable

The test bench setup is shown in the following picture:

Test Setup for HDMI 2.1 cable measurement

The following internal eye diagram is for a 2m HDMI 2.1 cable, the signal is running at 10Gbps. The transmitter side De-emphasis is set at -3 dB.

Internal Eye diagram

5.5       HSD Cable (Single-Ended Connection)

The following test is for HSD cable. 2 cables with lengths of 3 meters and 8 meters are tested. The insertion loss is measured as shown in the following pictures:

Sdd21：HSD Cable: 3 m (RG316) insertion loss

Sdd21 HSD Cable: 8 m (RG316) insertion loss

The test bench setup is shown in the following picture:

The following left-side internal eye diagram is for a 3m HSD cable, the signal is running at 8Gbps. The transmitter side De-emphasis is set at -1.94 dB.

The right-side internal eye diagram is for an 8m HSD cable, the signal is running at 6Gbps. The transmitter side De-emphasis is set at -1.94 dB.

5.6 Fiber Optic Cable

The last test is for the optical cable. The cable is SFP-FC16G-SW-CSC, shown in the following picture. It is 10meters long.

The internal eye diagram shows that the signal can run at 12Gbps. The transmitter side De-emphasis is set at -1.94 dB. Please note that on this test, the performance can be influenced by the electrical interfaces of the optical module.

6 Summary and Conclusion 

The results demonstrate that the GW5AT SerDes channel performance is more sensitive to insertion loss than raw cable length. Among the tested configurations:

• The ISI board setup yielded the highest performance (up to 12 Gbps).
• Fiber optics offered comparable performance with superior length capability.
• HDMI and HSD cables showed lower maximum data rates, limited by signal integrity constraints at extended lengths.
• Cable quality, gauge, and interconnect interfaces play a critical role in high-speed serial transmission performance.
  
  

Here is the table that summarizes the test results for the cables measured:

This evaluation provides a foundational reference for system designers choosing appropriate transmission media for applications involving GW5AT SerDes technology.

Support and Feedback

GOWIN Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.

Website: www.gowinsemi.com

E-mail：support@gowinsemi.com

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