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GOWIN ISP (Image Signal Processor)

GOWIN now offers an Image Signal Processor (ISP) pipeline and AE/AWB coprocessor which accepts a raw Bayer input stream generated by image sensor and outputs RGB stream with improved image quality for display or recognition purposes. The ISP takes the pixel data in Bayer format and adjusts it through CFA, CCM, and Gamma correction modules, and AEAWB module based on accumulated data in the statistics and histogram engines to provide a clear image that is balanced in color and brightness.

 

 

Gowin’s Image Signal Processor IP can be combined with other IP’s in Gowin’s IP core generator to develop a completely System on Chip (SoC) for new and existing video and imaging products

 

 

 

Features 

  • Supports 4 types of sensor alignments(BGGR, GBRG, GRBG, RGGB), and 8bit/10bit image data.
  • Support all kinds of resolution(VGA, 720p, 1080p, 2K, 4K).
  • Four independent ISP sub-blocks
    • AEAWB to automatically adjust the white balance and exposure.
    • CFA to complete the conversion of Bayer's image to RGB image.
    • CCM to achieve color correction.
    • GAMMA to achieve non-linear operations on the image gray value.

 

 

ISP Pipeline - Resource Utilization

Module Name

Register

LUT

ALU

DSP

BSRAM

SSRAM

CFA

597

570

693

0

6

0

CCM

578

56

0

6

0

0

GAMMA

76

22

0

0

1

0

AEAWB

1238

1153

748

6

3

4

Gowin's ISP solution consists of a set of image processing pipeline IP's as well as a coprocessor to monitor and control the pipeline in real time. The ISP pipeline IP's consist of four primary modules.

 


CFA (Color Filter Array) Debayer IP

The CFA (Color Filter Array) is a Debayer, which interpolates adjacent pixels to provide a three component RGB output. Gowin's CFA uses 5x5 interpolation.

 

 

CCM (Color Correction Matrix) IP

The Color Correction Matrix adjust incoming imaging data by providing gain and offset coefficients for each color component to maximize the range of digital values each color component can have as well as removing the influence one color component has on the other. This provides a method to calibrate colors of the image sensor.

 

 

Gamma Correction IP

Gamma correction provide a way to compensate for non-linear characteristics in display outputs as well as adjust contrast of the imaging stream.

 

 

AEAWB (Auto Exposure and Auto White Balance) IP

Auto exposure adjusts the luminance or brightness of the image so that it is not too dark or light when displayed.

Auto white balance adjusts color components to retain the same value for white color over the range of luminance or brightness). This way colors look similar over all luminance and exposures.

Auto Exposure and Auto White Balance use Histogram or Average Luminance sub-modules to learn about the color component values over the course of an image frame. This is read by a coprocessor such as an ARM Cortex-M via register map. The coprocessor then adjusts coefficient values of the imaging stream using an algorithm such as Gray World to adjust luminance and compensate for color variance.

 

Gowin's ISP IP is provided in conjunction with a complete ISP reference design and FPGA project for the DK-Start-GW2A55 Development Kit. The design includes several additional modules which are often used in conjunction with the ISP IP such as a MIPI CSI-2 interface to interface serial image sensors and depacketize image data, a frame buffer and DDR3 memory interface to store frames for post-processing and adjust frame rate, an I2C controller and PROM to initialize and adjust image sensor configuration and image cropping to obtain the image stream's active field of view. It also includes an ARM Cortex-M1 coprocessor to monitor and control the image processing pipeline.

 

 

 

 

 

Camera and Imaging SoC Reference Design - Resource Utilization

Module Name

Register

LUT

ALU

DSP

BSRAM

SSRAM

PLL

OV5647 Initialization

225

462

31

0

0

0

0

MIPI CSI-2 Interface

448

444

41

0

1

17

0

FOV Cropping

42

60

0

0

0

0

0

ISP Pipeline

2722

2013

1441

12

10

16

0

Video Frame Buffer

346

684

86

0

8

0

0

DDR3 Memory Interface

1729

1399

61

0

8

70

0

Scaler

892

623

68

0

18

4

0

Other

119

119

4

0

0

0

3

M1

2490

5694

162

3

64

20

0

Total

9165

11636

1894

13

109

131

3

 

Image Signal Processor (ISP) Demo and Explanation Video: Click here

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