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PRODUCTS
Low Power, High Performance, High Reliability
LITTLEBEE ®
  • Low Power Non-volatile FPGA
 
  • Best in class of Performance Cost Ratio
  • Small footprint
  • MIPI standard supported
  • Embedded SDRAM and pSRAM (GW1NR/1NSR only)

 

Based on 55nm LP technology, LittleBee® family offers instant-on, non-volatile, low power, intensive I/O and small footprint FPGA (smallest as 2.4x2.3mm). The family is ideal for high-performance bridging application and the first FPGA supports MIPI I3C and MIPI D-PHY standard in the industry. The LittleBee® family is also the first non-volatile FPGA with an embedded DRAM or pSRAM in the industry, which further reduces the broad space

  • User Flash (GW1N-1)

- 100,000 write cycles

- Greater than10 years Data Retention at +85°C

- Selectable 8/16/32 bits data-in and data-out

- Page size: 256 Bytes

- 3μA standby current

- Page Write Time: 8.2ms

 

  • User Flash (GW1N-2/4/6/9)

- Up to 1,792Kbits

- 10,000 write cycles

 

  • Lower Power Consumption

- 55nm embedded flash technology

- LV: supports 1.2V core voltage

- UV: built-in linear regulator, supports1.8V, 2.5V, and 3.3V core voltage input

- Clock dynamically turning on/ turning off

 

  • Multiple I/O Standards

- LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE

- Input hysteresis option

- Supports 4mA,8mA,16mA,24mA,etc. drive options

- Slew Rate option

- Output drive strength option

- Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option

- Hot Socket

 

  • High Performance DSP

- High performance digital signal processing ability

- Supports 9 x 9,18 x 18,36 x 36bit multiplier and 54bit accumulator;

- Multipliers cascading

- Registers pipeline and bypass

- Adaptive filtering through signal feedback

- Supports barrel shifter

 

  • Abundant Slices

- 4 input LUT (LUT4)

- Double-edge flip-flops

- Supports shift register and distributed register

 

  • Block SRAM with Multiple Modes

- Supports Dual Port, Single Port, and Semi Dual Port

- Supports bytes write enable

 

  • Flexible PLLs+DLLs

- Frequency adjustment (multiply and division) and phase adjustment

- Supports global clock

 

  • Built-in Flash Programming

-  Instant-on

-  Supports security bit operation

-  Supports AUTO BOOT and DUAL BOOT

 

  • Configuration

- JTAG configuration

- Up to 6 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

GW1N Family Table

 

Device GW1N-1 GW1N-2 GW1N-4 GW1N-6 GW1N-9
LUT4 1,152 2,304 4,608 6,912 8,640
Flip-Flop (FF) 864 1,728 3,456 5,184 6,480
ShadowSRAM S-SRAM(bits) 0 0 0 13,824 17,280
Block SRAM B-SRAM(bits) 72K 180K 180K 468K 468K
Number of B-SRAM  4 10 10 26 26
User Flash (bits) 96K 256K 256K 608K 608K
18 x 18 Multiplier 0 16 16 20 20
PLLs+DLLs 1+0 2+2 2+2 2+3 2+3
I/O Bank Number 4 4 4 4 4
Max. User I/O 121 205 205 273 273
Core Voltage (LV) 1.2V 1.2V 1.2V 1.2V 1.2V
Core Voltage (UV) - 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V

 


 

Package Options and Max I/O (* Refer latest datasheet for details)

 

Package Pitch (mm) Size (mm2) GW1N-1 GW1N-2 GW1N-4 GW1N-6 GW1N-9
CS30 0.4 2.4 x 2.3 23 - - - -
CM64 0.5 4.1 x 4.1 - - - 55 55
CS72 0.4 3.6 x 3.3 - 56 56 - -
QN32 0.5 5 x 5 25 23 23 - -
QN48 0.4 6 x 6 39 39 39 39 39
QN88 0.4 10 x 10 - 68 68 68 68
LQ100 0.5 16 x 16 78 78 78 78 78
LQ144 0.5 22 x 22 114 117 117 118 118
LQ176 0.4 22 x 22       144 144
MG160 0.5 8 x 8 116 128 128 128 128
PG204 1.0 17 x 17 116 - - - -
PG256 1.0 17 x 17 - 204 204 204 204
PG256M 1.0 17 x 17 - 204 204 - -
UG332 0.8 17 x 17 - - - 273 273

 

NEW Products

 

GW1NR-LV4MG81

4K LUTs FPGA with embedded 64 Mb pSRAM

 

The GW1NR-LV4MG81 is the first of GOWIN's embedded pSRAM memory products giving more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

 

Features:

  • 4K LUT FPGA Fabric
  • Embedded 64 Mb pSRAM
  • Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
  • Small package size:  81 pin PGA - 4.5mm x 4.5mm and 0.83mm thick!
  • Low power consumption
  • Up to 68 User I/O
  • Dual Boot FPGA
  • Remote upgradeable bitstream

 

GW1NSR-LX2CQN48

GOWIN's Full SoC solution with 2K LUT's and 32Mb pSRAM and Arm Cortex-M3

 

The GW1NSR-LX2CQN48 is a fully integrated device combining the features of the GW1NR family and GW1NS family into one chip.  

 

Features:

  • 2K LUT FPGA Fabric
  • Arm Cortex-M3 embedded with GOWIN's Shared Architecture
  • Embedded Memory - 32Mb high-speed pSRAM (8-bit wide data)
  • 2 User Flash Spaces
  • USB2.0
  • MIPI D-PHY I/O
  • 8 Channel ADC

 


 

GW1NR Family Table

 

Device GW1NR-4 GW1NR-6 GW1NR-9
LUT4 4,608 6,912 8,640
Flip-Flop (FF) 3,456 5,184 6,480
ShadowSRAM S-SRAM(bits) 0 13,824 17,280
Block SRAM B-SRAM(bits) 180K 468K 468K
Number of B-SRAM  10 26 26
User Flash (bits) 256K 608K 608K
Embedded SDRAM(bits) 64M 64M 64M
18 x 18 Multiplier 16 20 20
PLLs+DLLs 2+2 2+4 2+4
I/O Bank Number 4 4 4
Max. User I/O 205 273 273
Core Voltage (LV) 1.2V 1.2V 1.2V
Core Voltage (UV) 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V

 


 

Package Options and Max I/O (* Refer latest datasheet for details)

  

Package Pitch (mm) Size (mm2) GW1NR-4 GW1NR-6 GW1NR-9
QN88 QFN 0.4 10 x 10 68 - 68
LQ144         118

LittleBee® Documentation:

 GW1NS Family Table

 

Parameter GW1NS-2C
LUT4 1,728
FF 1,296
B-SRAM bits 72K
B-SRAM quantity 4
S-SRAM bits 2,304
User Flash bits 1M
PLLs + DLLs 1 + 2
OSC 1, +/- 5% accuracy
Hard Core Processor Arm Cortex M3
USB PHY USB2.0 PHY
ADC Channels 8
I/O Banks 4
Max. User I/O 95
Core Voltage 1.2V

 


 

Package Options with Max I/O (Refer to the latest datasheet for details)

 

Package Pitch(mm) Size(mm2) GW1NS-2C
CS36 0.4 2.4 x 2.4 31
QN32 0.5 5 x 5

25

QN32U 0.5 5 x 5 16
QN48 0.4 6 x 6 38
LQ144 0.5 22 x 22 95

 

GW1NSR Version includes:

  • 32M-bits of embedded pSRAM memory
  • 8-bit wide, 332Mbps data rates (166 MHz clock)

 

Embedded 32-bit RISC Microprocessor

  • Arm Cortex-M3 (60 MHz)
  • 128K User Flash

 

Embedded ADC

  • 8 Channels
  • 12-bit SAR AD conversion
  • 1 MHz Slew Rate
  • Up to 16 MHz sampling clock

 

Flash Configuration

  • Supports 2 image files
  • Supports Dual Boot
  • Online Upgradeable
  • Remote Upgrade

 

Integrated Development Flow for both M3 Core and FPGA Programming

  • Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

 

Embedded USB2.0 PHY

  • 480 Mbps data speed
  • Type-C compatible

 

Fixed MIPI D-PHY I/O

  • I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution