Low Power, High Performance, High Reliability

NEW Product




GOWIN Semiconductor now offers a solution of implementing configurable RISC-V IP in GW-2A FPGA. Here, the configurable RISC-V IP Core and System is a 32-bit RISC-V Microprocessor & Peripheral System with the following list of Architecture Structure and feature set:


Self Photos / Files - risc v pic


 The GOWIN Development Platform combines the RISC-V Microprocessor SW design flow and FPGA HW Design flow as a fully integrated single toolchain consisting of all GOWIN device model libraries and software driver libraries needed to program the GW2A-18/55 FPGA hosting with the configurable RISC-V & System Peripheral. The platform supports Application software compiling, linking, in-circuit-emulation/debugging on behalf of the embedded RISC-V microprocessor as well as synthesis and place & route of the FPGA design embedded with the RISC-V & System Soft IP.


Self Photos / Files - risc v pic 1

A Development Board is also available to be used in conjunction with the GOWIN programming tools for implementing RISC-V Microprocessor & Peripherals System in FPGA-SoC Design.


Self Photos / Files - risc v pic 2


RISC-V for GW2A Release – Software Package and Documentation:

  1. Go to
  2. Click “Download GOWIN EDA (Registration is required)
  3. Choose Windows or Linux
  4. Download Two Software Packages a. Download the Gowin_YunYuan_V1.8.1.01Beta(_win or _linux) or later b. Under “RISC V for GW2A Release Package”, click on the Dropbox link and download RISC-V for GW2A Release Package.
  5. Go to and Click on “Apply License” for the GOWIN EDA FPGA Design License.
  6. Go to and fill out form. Under “Enquiry” type “Request for AndeSight RDS for GOWIN SW Tool Chain License”.



Arora® Family is designed to offer the best-in-class performance cost ratio FPGA. With abundant logic, high-performance DSP resources and high speed I/O, the family is optimized for co-processing to offload the application processor on intensive computation tasks. The Arora® family is also the first FPGA with embedded pSRAM in the industry, which gives customers more usable device I/O.


  • Lower Power Consumption
    - 55nm SRAM technology
    - Core voltage: 1.0V
    - Clock dynamically turning on/ turning off


  • Multiple I/O Standards
    - Input hysteresis option
    - Supports 4mA, 8mA, 16mA, 24mA,etc. drive options
    - Slew Rate option
    - Output drive strength option
    - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    - Hot Socket


  • High Performance DSP
    - High performance digital signal processing ability
    - Supports 9 x 9,18 x 18,36 x 36bit multiplier and 54bit accumulator;
    - Multiplier cascading
    - Registers pipeline and bypass
    - Adaptive filtering through signal feedback
    - Supports barrel shifter


  • Abundant Slices
    - 4 input LUT (LUT4)
    - Double-edge flip-flops
    - Supports shift register and distributed register Block SRAM with Multiple Modes
    - Supports Dual Port, Single Port, and Semi Dual Port
    - Supports bytes write enable Flexible PLLs+DLLs
    - Frequency adjustment (multiply and division) and phase adjustment
    - Supports global clock Configuration
    - JTAG configuration
    - 6 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT
    - Data stream file encryption and security bit settings

GW2A Family Table


Device GW2A-18 GW2A-55
LUT4 20,736 54,720
Flip-Flop (FF) 15,552 41,040
Shadow SRAM S-SRAM(bits) 41,472 109,440
Block SRAM B-SRAM(bits) 828K 2,520K
Number of B-SRAM 46 140
18 x 18 Multiplier 48 40
PLLs+DLLs 4²+4 6+4
I/O Bank Number 8 8
Max. User I/O 319 607
Core voltage 1.0V 1.0V



Package Options and Max I/O (* Refer to the latest datasheet for details)


Package Pitch (mm)


GW2A-18 GW2A-55
QN88 0.4 10 x 10 66(22)  
LQ144 0.5 22 x 22 119(34) -
MG196 0.5 8 x 8 114(39)  
PG256 1.0 17 x 17 207(73) -
PG256S 1.0 17 x 17 192(72)  
PG484 1.0 23 x 23 319(77) 319(75)
PG672 1.0 27 x 27 384 384
PG1156 1.0 35 x 35 - 607(96)

GW2AR Family Table


Device GW2AR-18
LUT4 20,736
Flip-Flop (FF) 15,552
Shadow SRAM S-SRAM(bits) 41,472
Block SRAM B-SRAM(bits) 828K
Number of B-SRAM  46
DDR SDRAM (LQ176 pkg only) 128M
18 x 18 Multiplier 48
PLLs+DLLs 4+4
I/O Bank Number 8
Max. User I/O 140
Core voltage 1.0V



Package Options and Max I/O (* Refer to the latest datasheet for details)



Package Pitch (mm) Size(mm2) Max I/O pSRAM (Mb)
LQ144 0.4 22 x 22 120(34) 64 
QN88 0.4 10 x 10 66(22) 64 
LQ176 0.4 22 x 22 140(44)       128 DDR SDRAM

Arora ® Documentation

Coming Soon.